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21.
An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.  相似文献   
22.
Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.  相似文献   
23.
In their previous work, the authors have developed a method for selecting features based on the analysis of class regions approximated by hyperboxes. They select features analyzing class regions approximated by ellipsoids. First, for a given set of features, each class region is approximated by an ellipsoid with the center and the covariance matrix calculated by the data belonging to the class. Then, similar to their previous work, the exception ratio is defined to represent the degree of overlaps in the class regions approximated by ellipsoids. From the given set of features, they temporally delete each feature, one at a time, and calculate the exception ratio. Then, the feature whose associated exception ratio is the minimum is deleted permanently. They iterate this procedure while the exception ratio or its increase is within a specified value by feature deletion. The simulation results show that the current method is better than the principal component analysis (PCA) and performs better than the previous method, especially when the distributions of class data are not parallel to the feature axes  相似文献   
24.
A numerical evaluation is conducted of electric field distributions, phase constants, and attenuation constants of the lowest eigenmode in the general class of uniformly bent circular hollow waveguides. The analysis is based on a scalar equation, and numerical results are compared with those of existing approximate theories. Normalized forms of attenuation constants are presented for the parallel and perpendicular polarizations to the bending plane by using structural and material parameters. For sharply bent waveguides, useful and simple expressions are derived for the attenuation constants of the TE and TM modes in the corresponding slab geometry with suitable weighting parameters  相似文献   
25.
Carbon-supported La1−xSrxMnO3 (LSM/C) was prepared by reversible homogeneous precipitation method, and its catalytic activities for oxygen reduction under the existence of ethylene glycol (EG) were investigated by using rotating disk electrode. LSM/C exhibited the high activity for oxygen reduction irrespective with the presence of EG, indicating that EG is not oxidized by LSM/C at the cathode side in the present system. Consequently, LSM/C can serve as a cathode catalyst in alkaline direct alcohol fuel cells with no crossover problem. Performance test for fuel cells operation also supported these results and showed cathodic polarization curves were not affected by the concentration of EG supplied to anode even at 5 mol dm−3.  相似文献   
26.
This paper proposes a tactile-sensing mechanism for a robot. The mechanism is composed of a force-sensor device and an end-effector of shell shape. Since the end-effector plays the role of an outer shell, a force can be sensed at any position on the body. Due to the aspect of its intrinsic contact sensing, position of the single contact point is calculable without any sensor array. Another advantage is that the six-axis resultant force is measurable. This paper shows that the mechanism is also available for the end-effector with an angulated shape. The only condition for the shape is to be a convex hull. Some experimental results evaluate sources of error in practical measurement and show the validity of the proposed mechanism.  相似文献   
27.
We fabricated a 1-GHz-spaced 16-channel arrayed-waveguide grating (AWG) by using a new AWG configuration where the path of each arrayed waveguide winds backward and forward across a 4-in diameter wafer without crossing any other waveguides. The ultra-narrow (< 1 GHz) and stable transmission bands of this AWG can be used to construct a wavelength reference standard covering the S, C, and L bands in the dense wavelength-division-multiplexing network systems whose frequency deviation is /spl plusmn/160 MHz.  相似文献   
28.
We have compared experimentally the transmission performance of return-to-zero differential phase-shift keying (RZ-DPSK) with RZ-ON-OFF keying (OOK), nonreturn-to-zero differential phase-shift keying (NRZ-DPSK), and NRZ-OOK for 100/spl times/10-Gb/s transmission with a spectral efficiency of 0.22 b/s/Hz over transoceanic distances. The Q degradation of the RZ-DPSK after transmission over 9180 km was 3 dB greater than that of RZ-OOK. The experimental results clearly showed the major cause of degradation for DPSK is not cross-phase modulation but self-phase modulation. The calculated nonlinear phase noise, i.e., the Gordon-Mollenauer effect, agreed with the experimental results. A distributed-Raman-amplifier assisted erbium-doped-fiber-amplified transmission line acted well in reducing the nonlinear phase noise.  相似文献   
29.
Planar defects, like anti-phase boundaries (APBs) and stacking faults (SFs), are reduced by growing 3C-SiC on undulant-Si whose entire surface is covered with countered slopes oriented in the [1 1 0] and directions. During the initial 3C-SiC growth, APBs are eliminated on each slope of an undulation. Then, one kind of SF self-vanishes. However, another kind of SF remains on the 3C-SiC surface, although its density is gradually reduced with increasing SiC thickness by combining with a counter-SF. The leakage current of a pn diode fabricated homo-epitaxially on 3C-SiC is roughly proportional to the SF density before homo-epitaxial growth. The viability of 3C-SiC grown on undulant-Si for semiconductor devices is discussed by reviewing recent reports on various MOS-FETs using it as the substrate. The key issue in the fabrication of a MOS-FET as a power-switching device operated at high-voltage is to reduce the leakage-current at the pn junction, thereby eliminating SFs.  相似文献   
30.
An estimate has been made of the feasibility of a metallurgical purification process, the NEDO (New Energy and Industrial Technology Development Organization) melt‐purification process, for manufacturing solar‐grade silicon from metallurgical‐grade silicon. Equipment has been developed to pilot manufacturing plant scale. The system comprises an electron‐beam furnace for phosphorus removal and a plasma furnace for boron removal. Each furnace has a mold for directional solidification to remove metallic impurities. The concentration of each impurity in the silicon ingot purified through the whole process satisfied the solar‐grade level. The Solar‐grade silicon produced showed p‐type polarity and resistivity within the range 0·5–1·5 Ω cm. Copyright © 2001 John Wiley & Sons, Ltd.  相似文献   
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