PROUD: a sea-of-gates placement algorithm

An efficient method is proposed for placing modules in large and highly complex sea-of-gates chips that include preplaced I/O pads and macrocells. PROUD repeatedly solves sparse linear equations. A resistive network analogy of the placement problem and convexity of the objective function are key concepts in this algorithm. The algorithm was tested on nine real circuits. For a triple-metal-layer, 100000-gate sea-of-gate design with 26000 instances, the constructive phase took 50 minutes on a VAX 8650 and yielded excellent results for total wire length. Extensions of the method are considered     

The effects of 3-MeV proton radiation on an aromatic polysulfone

3-MeV proton beam irradiation studies have been carried out on a commercial aromatic polysulfone (Udell 1700). Physical and mechanical property changes have been monitored as a function of dose. Chemical and spectroscopic analyses have also been performed on the irradiated samples. Results have been compared to those from previous studies with electrons and γ-radiation. A mechanism of proton-induced degradation is proposed.     

New insensitive notch and allpass filters with single current follower

New second-order notch and allpass filters using a single current follower are proposed. The filters use five passive RC elements. Both the active and passive sensitivities are very low. The natural frequencies and the quality factors of the proposed filters are insensitive to the current tracking error of the current follower. Simulation results which agree with the theoretical analysis are obtained.<>     

A content addressable memory management unit with on-chip datacache

The design of a single chip (WE-32201) that includes both a content-addressable memory-based management unit and a large data/instruction cache is described. The chip belongs to AT&T's WE-32200 chip set and is fabricated using a 1 μm twin tub CMOS process. It boosts the performance of the entire chip set significantly by providing high memory bandwidth and virtual-memory-management support. The combination of high-performance circuit design and system architectural design techniques makes the chip a major enhancement to the chip set     

Composition of flavonoids and phenolic acids in Glycin tomentella Hayata cultivated in various soils

A high-performance liquid chromatography (HPLC) method was developed to simultaneously separate 12 phenolic acids and 21 flavonoids. The separation was performed with a C₁₈ column and a binary gradient solvent system consisting of methanol and water with 9% glacial acetic acid. The peak resolutions (Rs) were 0.51–12.41 and separation factors (α) were all higher than 1. The method was used to survey these phenolic components in Glycin tomentella Hayata. Diadzein was the major flavonoid in the leaves and roots, and gentisic acid and ferulic acid were the major phenolic acids in the leaves. Amounts of phenolic acids and flavonoids in the leaves from varied soil cultivations were in the order: loam > sand > red loamy sand. Flavonoid amounts in the roots also showed the same trend; however, phenolic acid amounts were low and did not present significant differences. Overall, the roots had much higher phenolic contents than the leaves.     

Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform

Due to recent advances in high dynamic range (HDR) technologies, the ability to display HDR images or videos on conventional LCD devices has become more and more important. Many tone-mapping algorithms have been proposed to meet this end, the choice of which depends on display characteristics such as luminance range, contrast ratio and gamma correction. An ideal HDR tone-mapping processor should have a robust core functionality, high flexibility, and low area consumption, and therefore an ARM-core-based system-on-chip (SOC) platform with a HDR tone-mapping application-specific integrated circuit (ASIC) is suitable for such applications. In this paper, we present a systematic methodology for the development of a tone-mapping processor of optimized architecture using an ARM SOC platform, and illustrate the use of this novel HDR tone-mapping processor for both photographic and gradient compression. Optimization is achieved through four major steps: common module extraction, computation power enhancement, hardware/software partition, and cost function analysis. Based on the proposed scheme, we present an integrated photographic and gradient tone-mapping processor that can be configured for different applications. This newly-developed processor can process 1,024 × 768 images at 60 fps, runs at 100 MHz clock and consumes a core area of 8.1 mm² under TSMC 0.13 μm technology, resulting in a 50% improvement in speed and area as compared with previously-described processors.     

Clustering Multiple Time Series with Structural Breaks

Time series clustering pattern could change over time. In this article we develop a new Bayesian approach to handle clustering analysis of multiple time series with structural breaks. The number of breaks is treated as a random variable, with group membership and group‐specific parameters allowed to change on these breaks. Group‐specific parameters in each regime can be integrated analytically, so we only have a small number of parameters to be handled by posterior simulation. We further discuss prediction, identification, clustering, and detection of the number of groups. Using Monte Carlo simulation, we document the performance of the proposed approach in statistical efficiency, forecasting, and detection of the structural breaks. An application on quarterly industrial production growth rates of 21 countries links regimes to historical business cycles. Prediction performance and economic gains are illustrated based on the proposed method.     

Manifestations of strain-relaxation in the structure of nano-sized Co-2 × 2 islands grown on Ag/Ge(111)-√3 × √3 surface

We have examined strain-relaxation of Co-2 × 2 islands grown on the Ag/Ge(111)-√3 × √3 surface by analyzing scanning tunneling microscopy images. We have found that the Co-2 × 2 islands commonly adopt a more compact arrangement as compared to that of the Ge(111) substrate, however they differ in a degree of an atomic compactness. We have not found a distinct relation between strain-relaxation and the island height. Three groups of islands have been identified upon analyzing a correspondence between strain-relaxation and the island size: (i) small islands (not bigger than 80 nm²) with a high atomic compactness, displaying fixed inter-row distances, (ii) small islands with unfixed distances between atomic rows, and (iii) big islands (bigger than 80 nm²) with fixed inter-row distances, but with a less compact atomic arrangement compared to that of the first two groups. We propose a model to account for the relation between the relaxation and the island size.