Linearized microring-loaded Mach-Zehnder modulator with RF gain

A linearized modulator based on the Mach-Zehnder interferometer (MZI) loaded with a second-order allpass microring resonator is proposed and analyzed. The device is shown to exhibit much smaller intermodulation distortion than standard Mach-Zehnder modulators, thus greatly enhancing the device dynamic range. Gain effect associated with the microring resonance results in a modulator transfer function with high slope efficiency and large RF gain. Moreover, combined with the use of a highly electrooptic polymer, the high slope efficiency allows for the possibility of realizing modulators with subvolt drive voltage. The detrimental effect of loss in the microring resonators on device performance is also investigated and a design approach to mitigate its effect is presented. The proposed modulator can be linearized to any arbitrary nth order by loading the MZI with a higher order allpass microring resonator.     

Municipalities as a Driver for Wireless Broadband Access

Municipalities can form a driving force behind the deployment of new telecom infrastructure. While a telecom operator focuses on direct (financial) profits, a municipality is mainly interested in the social benefits for its inhabitants. In this paper, we evaluate a wireless municipality network from both a technical and an economic point of view. WiFi and WiMAX are considered as the most suited technologies for this purpose. A detailed techno-economic study has been performed including forecasting of the user adoption, dimensioning of the wireless network and modelling the related costs and revenues. The trade-off between installing a high number of relatively cheap WiFi access points, and a smaller number of more expensive WiMAX base stations for delivering full coverage is investigated in several scenarios.

Use of Deeply Integrated GPS/INS Architecture and Laser Scanners for the Identification of Multipath Reflections in Urban Environments

This paper investigates the constructive use of multipath reflections of Global Positioning System (GPS) signals for navigation in urban environments. Urban navigation applications are generally characterized by a significant presence of multipath signals. In order to maintain reliable and accurate navigation capabilities, it is critical to distinguish between direct signal and multipath. At the same time, multipath reflections can be exploited as additional measurements for those cases where the number of direct path satellites is insufficient to compute the navigation solution. The paper develops a method for the identification of multipath reflections in received satellite signals: i.e., multipath is separated from direct signal and a line-of-site between the GPS receiver and a multipath reflecting object is determined. Once multipath reflections are identified, they can be used constructively for navigation. The method presented in the paper exploits an open-loop batch-processing GPS receiver, laser scanner and inertial navigation system (INS) to identify multipath reflections in received satellite signals. Experimental GPS, inertial and laser scanner data collected in real urban environments are applied to demonstrate identification of multipath reflections.     

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

This investigation proposes a novel radix-4² algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4² single delay feedback path (R4²SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8times8 2D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8times8 2D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 times 8 2D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mum CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.     

On-Line Harmonic Analysis as a Diagnostic Design and Control Tool for Power Systems Feeding Arc Furnaces, Thyristor-Controlled Mill Drives, and Power Factor Correction Equipment

Microprocessor-based signal processing equipment for frequencies up to 20 kHz have become compact and fast enough to allow direct on-line real-time analysis on power systems to determine behavior. A case study is presented for a small steelworks operating a 25-MVA open arc furnace, installing 6.5 MVA of thyristor control equipment and further power factor correcting equipment and harmonic filters on a system with ill-defined parameters, low short- circuit capacity, and already containing power factor correcting capacitors tuned at the third harmonic. Discrete spectrum analysis equipment, microprocessor-based and coupled via IEEE-bus to a microcomputer system, was used to do on-line analysis at various points in the system. The high-speed system enabled sophisticated signal processing to yield even and uneven harmonics, stochastic components, system parameters and resonances and mutual interference. It is shown how this is used to rectify problems in the system, adapt equipment, and design power factor and filter equipment.     

Biasing a differential pair in low-voltage analog circuits: a systematic approach

This paper deals with a systematic approach to the common mode and the differential mode biasing of a differential transistor pair. Four different variants will be shown, two of these variants show practical importance; a practical circuit of one of these variants turns out to be the traditional long-tailed pair. This variant is mainly suited, if the input signal operates at voltage level, whereas another variant has great advantages if operation at current level occurs. Besides, the latter variant turns out to be very favorable in circuits operating with a single low supply voltage. Two practical circuits based on this variant are given.     

High-performance InP/InGaAs heterojunction bipolar transistors with highly carbon-doped base grown by chemical beam epitaxy

InP/In/sub 0.53/Ga/sub 0.47/As heterojunction bipolar transistors (HBTs) using a highly carbon-doped base are reported. High carbon doping has been achieved by chemical beam epitaxy (CBE). The resulting hole concentration in the carbon-doped base is as high as 7*10/sup 19//cm/sup 3/. To the authors' knowledge, this is the highest doping level reported using carbon. HBTs with a 20 AA spacer layer exhibited nearly ideal I-V characteristics with collector and base current ideality factor of 1.018 and 1.037, respectively. Current gain and breakdown voltage BV/sub CEO/ were 7 and 6 V, respectively.<>     

Subspace-based signal analysis using singular value decomposition

A unified approach is presented to the related problems of recovering signal parameters from noisy observations and identifying linear system model parameters from observed input/output signals, both using singular value decomposition (SVD) techniques. Both known and new SVD-based identification methods are classified in a subspace-oriented scheme. The SVD of a matrix constructed from the observed signal data provides the key step in a robust discrimination between desired signals and disturbing signals in terms of signal and noise subspaces. The methods that are presented are distinguished by the way in which the subspaces are determined and how the signal or system model parameters are extracted from these subspaces. Typical examples, such as the direction-of-arrival problem and system identification from input/output measurements, are elaborated upon, and some extensions to time-varying systems are given     

Performance analysis of linear MIMO equalizers for multitone DS/SS systems in multipath channels

In [11] the combination of multitone modulation with direct sequence spectrum spreading has been introduced. The performance of a correlation receiver has been evaluated for a multipath channel. In [12] the analysis has been extended to the presence of a multiple access interference. In the present paper we analyze the equalization problem of such a system for a single user scenario. In order to understand the potential of the system we first investigate the steady-state behavior of the MIMO equalizer for an MMSE design. The investigation is carried out for an equalizer following a receiver made of a bank of filters matched to both the symbol shape and the channel, which is a two-path channel. Assuming BPSK symbols an exact expression of the bit error probability before and after equalization is obtained in the form of an integral by means of the characteristic function method. Next adaptive LMS and RLS structures are proposed. The performance of the RLS algorithm is demonstrated.Part of this work has been presented at ICC '95, Seattle, June 1995.This author would like to thank the Belgian NSF for its financial support.This author is a Research assistant of FRIA.     

A power-efficient channel coder/decoder chip for GSM terminals

A compact power- and computing-delay-efficient channel codec chip for the Pan-European digital cellular radio (GSM) system is presented. This key component for the hand-portable mobile station, mainly implementing GSM Recommendation 5.03 on a full duplex basis, is accomplished through a dedicated architecture and application tailored memories. An important effort was made to increase the testability of the design; the sequentiality, the low pin count, and the presence of embedded macro functions implied the need for internal scan and BIST techniques. Full scan design and self-test facilities, supported by automatic test pattern generating software, resulted in time- and coverage-efficient testing. The chip is fabricated in a double-metal 1.2-μm CMOS technology, using a cell-based design approach incorporating memory and programmable array macro blocks. A full-rate speech channel block is decoded in less than 1.8 ms and typical average in-system power consumption does not exceed 10 mW