An iterative FEM for scattering by a 3-D cavity-backed aperture

A finite-element method (FEM)-based hybrid method (or iterative FEM) is successfully applied to a three-dimensional (3-D) scattering problem without the effect of internal resonance. With only a small number of meshes around a 3-D scatterer, this FEM is shown to give an accurate result through several iterative updates of the boundary conditions. To confirm the efficiency of this method, scattering from a 3-D cavity-backed aperture is analyzed and the results obtained are compared with the same obtained by another conventional method     

Effect of External Viscous Load on Head Movement

Quantitative measurements of horizontal head rotation were obtained from normal human subjects intending to make "time optimal" trajectories between targets. By mounting large, lightweight vanes on the head, viscous damping B, up to 15 times normal could be added to the usual mechanical load of the head.     

A single capacitor loop filter phase-locked loop with frequency voltage converter

A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 μm CMOS process show that the phase noise is ?109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.     

Neuro-Glia-Vascular-on-a-Chip System to Assess Aggravated Neurodegeneration via Brain Endothelial Cells upon Exposure to Diesel Exhaust Particles

Air pollution induces neurodegeneration, including cognitive deficits, neuroinflammation, and disruption of the blood–brain barrier. The mechanisms underlying air pollution-mediated neurodegeneration have not yet been fully elucidated given the limited knowledge on intercellular interactions. A brain-on-a-chip platform is presented comprising neurons, glia, and brain endothelial cells (bECs; neuro-glia-vascular, NGV) and diesel exhaust particle (DEP)-induced neurodegeneration is evaluated with a particular focus on the intercellular interactions. DEP exposure in the NGV model yields Alzheimer's disease-like signatures, including amyloid beta accumulation, tau phosphorylation, hydrogen peroxide (H₂O₂)/reactive oxygen species (ROS) production, and neuronal cell death. bEC-secreted granulocyte-macrophage colony-stimulating factor (GM-CSF) stimulates microglial activation and the overproduction of H₂O₂/ROS in microglia, suggesting that the bEC-microglia-neuron is a neurodegeneration cascade. Pharmacological inhibition at each step of the cascade, including GM-CSF neutralization, microglial activation suppression, and ROS scavenging, prohibits neurodegeneration in the NGV model. Therefore, intercellular interactions should be further studied of air pollution-induced neurodegeneration.     

Unleashing the Potential of Sodium-Ion Batteries: Current State and Future Directions for Sustainable Energy Storage

Rechargeable sodium-ion batteries (SIBs) are emerging as a viable alternative to lithium-ion battery (LIB) technology, as their raw materials are economical, geographically abundant (unlike lithium), and less toxic. The matured LIB technology contributes significantly to digital civilization, from mobile electronic devices to zero electric-vehicle emissions. However, with the increasing reliance on renewable energy sources and the anticipated integration of high-energy-density batteries into the grid, concerns have arisen regarding the sustainability of lithium due to its limited availability and consequent price escalations. In this context, SIBs have gained attention as a potential energy storage alternative, benefiting from the abundance of sodium and sharing electrochemical characteristics similar to LIBs. Furthermore, high-entropy chemistry has emerged as a new paradigm, promising to enhance energy density and accelerate advancements in battery technology to meet the growing energy demands. This review uncovers the fundamentals, current progress, and the views on the future of SIB technologies, with a discussion focused on the design of novel materials. The crucial factors, such as morphology, crystal defects, and doping, that can tune electrochemistry, which should inspire young researchers in battery technology to identify and work on challenging research problems, are also reviewed.     

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.     

On the selective counting of third-order products

A practical and efficient method is presented for the counting of third-order products generated by an arbitrary number of carriers with arbitrary power spectral shapes. In particular, three selective counting procedures (i.e. sorting by position, sorting by position and group, and sorting by position, group, and kind) are introduced in a systemic way, based upon a discrete third-order Volterra model. The advantage of the counting algorithm is that (1) the algorithm provides the exact counting of third-order products of all eleven possible groups; (2) the counting process requires only two multiplications for the selective counting of third-order products at each position, and the algorithm, which is thus efficient, can be easily implemented     

Effective Polysulfide Rejection by Dipole‐Aligned BaTiO3 Coated Separator in Lithium–Sulfur Batteries

Although the exceptional theoretical specific capacity (1672 mAh g^?1) of elemental sulfur makes lithium–sulfur (Li–S) batteries attractive for upcoming rechargeable battery applications (e.g., electrical vehicles, drones, unmanned aerial vehicles, etc.), insufficient cycle lives of Li–S cells leave a substantial gap before their wide penetration into commercial markets. Among the key features that affect the cyclability, the shuttling process involving polysulfides (PS) dissolution is most fatal. In an effort to suppress this chronic PS shuttling, herein, a separator coated with poled BaTiO₃ or BTO particles is introduced. Permanent dipoles that are formed in the BTO particles upon the application of an electric field can effectively reject PS from passing through the separator via electrostatic repulsion, resulting in significantly improved cyclability, even when a simple mixture of elemental sulfur and conductive carbon is used as a sulfur cathode. The coating of BTO particles also considerably suppresses thermal shrinkage of the poly(ethylene) separator at high temperatures and thus enhances the safety of the cell adopting the given separator. The incorporation of poled particles can be universally applied to a wide range of rechargeable batteries (i.e., metal‐air batteries) that suffer from cross‐contamination of charged species between both electrodes.     

S/W Based Frame‐Level Synchronization for Irregular Screen Processing System

A multi‐screen environment provides a new opportunity for digital signage applications, where various irregularly shaped screens are employed as an effective means for advertisements and information. A formation method applicable to numerous irregularly shaped screens is proposed to provide a new perspective on digital signage applications. The crucial part of the proposed method comes from the geometric sensing of each screen and the formation of a virtual screen where geometrically aligned content extraction and encoding are employed for content transmission to each screen. In addition, a software‐based synchronization method for the proposed system is proposed to address the frame‐level synchronization between screens. The experimental results of the proposed method show an improved performance of the frame‐level synchronization, where the inconsistency between frames is not identified.