Neighbor discovery in wireless networks with sectored antennas

Directional antennas offer many potential advantages for wireless networks such as increased network capacity, extended transmission range and reduced energy consumption. Exploiting these advantages requires new protocols and mechanisms at various communication layers to intelligently control the directional antenna system. With directional antennas, many trivial mechanisms, such as neighbor discovery, become challenging since communicating parties must agree on where and when to point their directional beams to communicate.In this paper, we propose a fully directional neighbor discovery protocol called Sectored-Antenna Neighbor Discovery (SAND) protocol. SAND is designed for sectored-antennas, a low-cost and simple realization of directional antennas, that utilize multiple limited beamwidth antennas. Unlike many proposed directional neighbor discovery protocols, SAND depends neither on omnidirectional antennas nor on time synchronization. SAND performs neighbor discovery in a serialized fashion allowing individual nodes to discover all potential neighbors within a predetermined time. SAND guarantees the discovery of the best sector combination at both ends of a link, resulting in more robust and higher quality links between nodes. Finally, SAND reliably gathers the neighborhood information in a centralized location, if needed, to be used by centralized networking protocols. The effectiveness of SAND has been assessed via simulation studies and real hardware implementation.     

Characterizing pairwise contact patterns in human contact networks

We use a counting process representation of the pairwise contact process to analyze pairwise contact patterns. Studying two real-world traces, we find that the pairwise contact patterns have three characteristics. First, human contact patterns are influenced by daily and weekly cycles of activity. Second short time intervals with intensive contact event (bursts) are separated by long periods with few contact events. Third, the pairwise contact process exhibits long range dependence. We introduce a Markov modulated Poisson process (MMPP) as a flexible model for pairwise contact process exhibiting both regular structure and irregular bursts of activity. Using standard statistical techniques, we demonstrate that the proposed model is consistent with the empirical data. Our work has significant implication for mobility modeling and performance analysis in human contact networks.     

Development, implementation, and testing of fault detection strategies on the National Wind Technology Center’s controls advanced research turbines

The National Renewable Energy Laboratory’s National Wind Technology Center dedicates two 600 kW turbines for advanced control systems research. A fault detection system for both turbines has been developed, analyzed, and improved across years of experiments to protect the turbines as each new controller is tested. Analysis of field data and ongoing fault detection strategy improvements have resulted in a system of sensors, fault definitions, and detection strategies that have thus far been effective at protecting the turbines. In this paper, we document this fault detection system and provide field data illustrating its operation while detecting a range of failures. In some cases, we discuss the refinement process over time as fault detection strategies were improved. The purpose of this article is to share field experience obtained during the development and field testing of the existing fault detection system, and to offer a possible baseline for comparison with more advanced turbine fault detection controllers.     

Multiphase sinusoidal oscillators using second generation current conveyors

A voltage-mode Multiphase Sinusoidal Oscillator realized using Second Generation Current Conveyors and only grounded passive elements is introduced in this paper. The proposed topology is suitable for realizing oscillators with both odd and even number of phases without modifying the core of the topology. Only non-inverting Current Conveyors are required for the construction of the oscillator's topology and this is a benefit from the discrete component implementation point of view. The behavior of the proposed topology has been evaluated, through experimental results, in the cases of three and six-phase oscillators.     

Throughput and delay analysis of multi-channel wireless infrastructure networks

Wireless infrastructure networks (WINs) provide ubiquitous connectivity to mobile nodes in metro areas. The nodes in such backbone networks are often equipped with multiple transceivers to allow for concurrent transmissions in multiple orthogonal channels. In this study, we develop an analytical model for the estimation of the delay and throughput performance of wireless infrastructure networks employing slotted ALOHA channel access and slotted Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) over multiple channels. The analytical model, which takes into account the correlation due to multi-hop transmissions, approximates the performance observed through simulations accurately.     

Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters

Settling behavior of operational amplifiers is of great importance in many applications. In this paper, an efficient methodology for the design of high-speed two-stage operational amplifiers based on settling time is proposed. Concerning the application of the operational amplifier, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. As the effect of transfer function zeros has been taken into account, the proposed methodology becomes more accurate in achieving the desired specifications. Simulation results are presented to show the effectiveness of the methodology.     

Reducing leakage power with BTB access prediction

This paper investigates three architectural methods to reduce the leakage power dissipated by the BTB data array. The first method (called here window) periodically places the entire BTB data array into drowsy mode. A drowsy entry is woken up by the first access in the time interval and remains active for the remainder of the interval (window). There is an associated performance loss which is related to the size of the window, since there is a delay when a specific line must be woken up. The second method, awake line buffer (ALB), limits the number of active BTB entries to a predetermined maximum. While this reduces power dissipation it comes with a performance penalty that is relative to the size of the buffer. ALB, however, reduces the power dissipation of the data array more than the window method. The third method, 2-level ALB (2L-ALB), uses a two level buffer with the identical number of combined entries as the previous method. This method exploits the fact that many branches operate numerous times in a fixed sequence. By predicting the next BTB access, 2L-ALB achieves further reduction in leakage power without incurring any further performance loss, compared to the ALB method.     

Analog circuits optimization based on evolutionary computation techniques

This paper presents a new design automation tool, based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.     

Scaling of analog LDPC decoders in sub-100 nm CMOS processes

Analog implementations of digital error control decoders, generally referred to as analog decoding, have recently been proposed as an energy and area competitive methodology. Despite several successful implementations of small analog error control decoders, little is currently known about how this methodology scales to smaller process technologies and copes with the non-idealities of nano-scale transistor sizing. A comprehensive analysis of the potential of sub-threshold analog decoding is examined in this paper. It is shown that mismatch effects dominated by threshold mismatch impose firm lower limits on the sizes of transistors. The effect of various forms of leakage currents is also investigated and minimal leakage current to normalizing currents are found using density evolution and control simulations. Finally, the convergence speed of analog decoders is examined via a density evolution approach. The results are compiled and predictions are given which show that process scaling below 90 nm processes brings no advantages, and, in some cases, may even degrade performance or increase required resources.