An improved quantum-inspired evolutionary algorithm for coding resource optimization based network coding multicast scheme

This paper investigates how to minimize the required coding resources in network-coding-based multicast scenarios. An evolutionary algorithm (MEQEA) is proposed to address the above problem. Based on quantum-inspired evolutionary algorithm (QEA), MEQEA introduces multi-granularity evolution mechanism which allows different chromosomes, at each generation, to have different rotation angle step values for update. In virtue of this mechanism, MEQEA significantly improves its capability of exploration and exploitation, since its optimization performance is no longer overly dependant upon the single rotation angle step scheme shared by all chromosomes. MEQEA also presents an adaptive quantum mutation operation which is able to prevent local search efficiently. Simulations are carried out over a number of network topologies. The results show that MEQEA outperforms other heuristic algorithms and is characterized by high success ratio, fast convergence, and excellent global-search capability.     

Throughput and delay analysis of multi-channel wireless infrastructure networks

Wireless infrastructure networks (WINs) provide ubiquitous connectivity to mobile nodes in metro areas. The nodes in such backbone networks are often equipped with multiple transceivers to allow for concurrent transmissions in multiple orthogonal channels. In this study, we develop an analytical model for the estimation of the delay and throughput performance of wireless infrastructure networks employing slotted ALOHA channel access and slotted Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) over multiple channels. The analytical model, which takes into account the correlation due to multi-hop transmissions, approximates the performance observed through simulations accurately.     

Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

Statistical analysis of large on-chip power grid networks by variational reduction scheme

One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.     

Multiphase sinusoidal oscillators using second generation current conveyors

A voltage-mode Multiphase Sinusoidal Oscillator realized using Second Generation Current Conveyors and only grounded passive elements is introduced in this paper. The proposed topology is suitable for realizing oscillators with both odd and even number of phases without modifying the core of the topology. Only non-inverting Current Conveyors are required for the construction of the oscillator's topology and this is a benefit from the discrete component implementation point of view. The behavior of the proposed topology has been evaluated, through experimental results, in the cases of three and six-phase oscillators.     

功能性空气过滤材料及其应用

论述了功能性空气过滤材料的各种功能及功能性作用机理，并介绍了几种功能性滤料的特性和应用，提出了功能性滤料的发展方向。     

Design metal-dot based QCA circuits using SPICE model

This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE. In the second half part of the paper, SET and QCA co-design methodology is proposed and SET is used as a readout interface of the QCA cell array. The SET and QCA hybrid circuit is a promising nano-scale solution.     

数控拉线机控制系统的软件可靠性设计技术

为提高拉线工艺的可靠性,对控制系统的软件可靠性设计技术进行研究。分析数控拉线机的膛线自动加工过程,分别从中断的自动恢复技术、工艺参数与膛线方程绑定校验、刀具基准调整互锁保护技术、工艺循环完整性保证等方面进行设计。从系统调试及实际加工过程的长时间验证结果来看,整个工艺过程的数字化能得到很好的保证。     

一种自适应的太赫兹无线个域网高效定向MAC协议

针对现有太赫兹无线个域网定向MAC协议存在的波束训练开销和入网时延偏大以及Beacon, S-CAP时段时隙利用不足问题,该文提出一种自适应的定向MAC协议——AD-MAC,自适应地在静态场景下采用全网协同波束训练,在动态场景下节点基于历史信息快速回复波束训练帧,同时使用反向监听策略减小同扇区节点的帧碰撞概率,并且通过时隙复用在Beacon和S-CAP时段并行发送控制帧和数据帧。理论分析表明了AD-MAC协议的有效性,仿真结果显示：相较于ENLBT-MAC等典型协议,AD-MAC在静态场景下的波束训练开销和节点平均入网时延分别降低了约21.84%和22.70%,在动态场景下上述二指标则分别减小了约18.7%和13.07%。

     

电流型变参数同步混沌电路

本文运用微分动力学的基本理论,得到了基于蔡氏电路的同步混沌电路的数学模型,计算了此同步混沌电路的平均收敛速率．之后,用电流型器件ＯＴＡ（跨导运算放大器）综合了此同步混沌电路,并进一步从计算机仿真和实验两个方面分析了该同步混沌电路的收敛特性和参数灵敏度特性．