Analysis of demand‐priority access using a priority queue with server vacations and message dependent switchover times

In this paper, we analyse the message waiting times in a local area network (LAN) that uses the demand‐priority access method. This is a priority‐based round‐robin arbitration method where the central controller (the repeater) polls its connected ports to determine which have transmission requests pending and the requests' priority classes. We model it as a 2‐priority M/G/1 queue with multiple server vacations and switchover time between service periods. The service discipline is nonpreemptive and the length of the switchover time is dependent upon the priority class of the preceding message served as well as that of the message to be served next. We provide an approximate analysis for the waiting times of both message classes and derive expressions for the Laplace–Stieltjes transforms (LST) of the stationary distributions and the mean waiting times. We conclude with numerical and simulation results to show the applicability and accuracy of the analytical model. This revised version was published online in June 2006 with corrections to the Cover Date.     

Measurement and analysis of neutron-induced soft errors insub-half-micron CMOS circuits

Neutron-induced soft error rates (SERs) of subhalf-micron CMOS SRAM and Latch circuits were studied both experimentally and analytically to investigate cosmic ray neutron-induced soft errors (SEs). Because the neutron beam used in the measurement has an energy spectrum similar to that of sea-level atmospheric neutrons, our SER data corresponds to those induced by cosmic ray neutrons. The α-particle induced SERs were also measured for comparison with the neutron-induced SER's. Neutron-induced SEs occurred in both circuits. On the other hand, α-induced SEs occurred in SRAM, but not in the Latch circuits. The measured SERs agreed with simulated results. We discussed the significance of how cosmic ray neutrons affects CMOS circuits at ground level     

Effects of AsH3 surface treatment for the improvement of ultra-shallow area-selective regrown GaAs sidewall tunnel junction

Low-temperature (290°C) area-selective regrowth by molecular layer epitaxy (MLE) was applied for the fabrication of an ultra-shallow sidewall (50 nm) GaAs tunnel junction. Fabricated tunnel junctions have shown a record peak current density up to 35,000 A/cm². It is shown that the tunnel junction characteristics are strongly dependent on the sidewall orientation and the AsH₃ surface treatment conditions just prior to regrowth. The effects of AsH₃ surface treatment are discussed in view of the control of surface stoichiometry.     

Development of chip-on-flex using SBB flip-chip technology

A bare LSI chip mounted onto a flexible substrate is called chip-on-flex (COF). Companies and universities are desperately developing COF. In this paper, the development of COF using stud bump bonding (SBB) flip-chip technology will be introduced.So far, SBB technology has been adopted when ceramic or glass-epoxy is used as a substrate material for chip size packages (CSPs) and multi-chip modules (MCMs). Recently there is a great demand for developing SBB technology toward a flexible substrate.SBB technology needs to keep a flexible substrate flat during the assembly process. A flexible substrate was adhered to a flat carrier using a thermal release sheet in order to keep it flat. Since this thermal release sheet loses its adhesive strength by applying heat beyond 160°C, it is easy to peel off accomplished specimens from the flat carrier after assembling.SBB specimens were prepared using liquid crystal polymer (LCP) and polyimide (PI) as a flexible substrate. Reliability tests, such as pressure cooker test (PCT), thermal shock test (TST) and reflow soldering after moisture storage test, were carried out for these specimens. In PCT, both LCP and PI specimens passed as a result of using proper underfill for each substrate. In TST, both specimens also passed using the underfill selected in PCT. In reflow soldering after moisture storage test, LCP specimens passed, on the other hand PI specimens needed to be baked after moisture storage in order to pass the reflow.     

Measurement of slowly varying component in phase error distribution of a large-channel-spacing arrayed-waveguide grating

It has been difficult to measure the phase error distribution of a large-channel-spacing arrayed-waveguide grating (AWG) with optical low coherence interferometry (OLCI). In this reported work OLCI was successfully used to measure the slowly varying component in the distribution of a 1 THz-spaced AWG that was the primary filter in an ultra-high-density multi/demultiplexer. The spectral sidelobe of the AWG can be reduced by using the component to achieve the lowest possible accumulated crosstalk in the multi/demultiplexer.     

100 Å-thick tunnel junction by double impurity doping liquid phase epitaxy for V-band TUNNETT oscillation

The tunnel injection transit time (TUNNETT) diodes with p⁺p⁺n⁺n⁻n⁺ structure were fabricated by liquid phase epitaxy (LPE). About 100 Å tunnel junction (p⁺n⁺) was successfully prepared by the double impurity diffusion of Ge and S during LPE growth. Continuous wave (CW) oscillation was realized at 51.520 GHz in the V-band cavity with the phase noise of −60 dBc/Hz at 1 kHz bandwidth.     

Studies on solder bump electromigration in Cu/Sn–3Ag–0.5Cu/Cu system

This paper aims to understand the solder bump electromigration phenomenon in the Cu/Sn–3Ag–0.5Cu/Cu system. A temperature of 453 K with a current density of 10 kA/cm² was applied. A void nucleated at the highest current density point at the cathode. As the void grew along the cathode side, a solder depletion occurred on the opposite side of the electron entry point, resulting in an open failure. A unique purposely-designed 3D model simulation methodology provides a good understanding of the void nucleation and growth behavior. The temperature of the solder joint during the electromigration test was measured successfully by the resistance change in the junction line between the two joints.     

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-μm L_eff CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm×6.38-mm chip, organized as either 512 K word×8 b or 1 M word×4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V_cc and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V_cc to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time     

Soft error susceptibility mapping of DRAMs using a high-energy nuclear microprobe

Soft errors in 16 Mbit dynamic random access memories (DRAMs) have been investigated using proton microprobes at 400 keV with a spot size of 1 × 1 μm². The newly developed susceptibility mapping can reveal the correlation between the particle hit-position position and the susceptibility to soft errors in a DRAM. The cell-mode soft-errors were found to take place by the incidence of ions within 6 μm around a monitored cell. These errors would be induced by minority carrier diffusion in a lateral direction. This result manifests the possibility of multiple-bit errors by the incidence of an energetic particle.