3D model retrieval using principal plane analysis and dynamic programming

Three dimensional models play an important role in many applications; the problem is how to select the appropriate models from a 3D database rapidly and accurately. In recent years, a variety of shape representations, statistical methods, and geometric algorithms have been proposed for matching 3D shapes or models. In this paper, we propose a 3D shape representation scheme based on a combination of principal plane analysis and dynamic programming. The proposed 3D shape representation scheme consists of three steps. First, a 3D model is transformed into a 2D image by projecting the vertices of the model onto its principal plane. Second, the convex hall of the 2D shape of the model is further segmented into multiple disjoint triangles using dynamic programming. Finally, for each triangle, a projection score histogram and moments are extracted as the feature vectors for similarity searching. Experimental results showed the robustness of the proposed scheme, which resists translation, rotation, scaling, noise, and destructive attacks. The proposed 3D model retrieval method performs fairly well in retrieving models having similar characteristics from a database of 3D models.     

Robust pole clustering in a good ride quality region of aircraft for matrices with structured uncertainties

This paper presents a general analysis of robust pole clustering in a good ride quality region (GRQR) of aircraft for matrices with structured uncertainties. This region is an intersection of a ring and a horizontal strip, located in the left half-plane, which is a specific non-Ω-transformable region providing good ride quality of aircraft. The paper applies the Rayleigh principle along the norm theory to analyze robust pole clustering within this region since the generalized Lyapunov theory is not valid for non-Ω-transformable regions. Concerned uncertainties are structured/parametric uncertainties, including interval matrices. The results are useful for robust control analysis and design, especially, of robust good ride quality of aircraft, shuttles, vehicles and space station, as well as some industrial systems. An example of the F-16 dynamics for which GRQR is suitable is included to illustrate the results.     

Robot control and parameter estimation with only joint position measurements

Most adaptive control schemes for rigid robots assume velocities measurements to be available. Although it is possible to measure velocities by using tachometers, this increases costs and the signals delivered may be contaminated with noise. Since the use of encoders allows to read joint position pretty accurately, it is desirable to estimate joint velocities through an observer. This paper presents an adaptive scheme designed in conjunction with a linear observer. Boundedness of the estimated parameters and uniform ultimate boundedness for the tracking and observation errors are guaranteed. Experimental results are included to support the developed theory.     

基于FPGA和ARM的弹上相位自动微调控制器设计与实现

为了提高相位自动微调控制器的控制性能,针对某型导弹,提出并实现了以ARM+ FPGA双微处理器为核心的硬件设计方案,采用了模糊PID控制算法,通过优化步进电机控制模式,提高了相位自动微调控制器的控制精度,将步进电机的调整时间由800 ms缩短到100 ms以内;该方案已成功应用于某型弹上系统,实践证明,该设计方案成本低、可扩展性强,能够满足系统控制需求,具有较高的实用性,大大提高了装备维护效率.     

Blind estimation of the PN sequence in lower SNR DS-SS signals with residual carrier

This paper presents a method of singular value decomposition (SVD) plus digital phase lock loop (DPLL) to solve the difficult problem of blind pseudo-noise (PN) sequence estimation in low signal to noise ratios (SNR) direct sequence spread spectrum (DS-SS, DS) signals with residual carrier. Of course, the method needs to know the parameters of DS signal, such as the period and code rate of PN sequence. Firstly, the received signal is sampled and divided into non-overlapping signal vectors according to a temporal window, whose duration is two periods of PN sequence. Then, an autocorrelation matrix is computed and accumulated by the signal vectors one by one. The PN sequence with residual carrier can be estimated by the principal eigenvector of this autocorrelation matrix. Furthermore, a DPLL is used to deal with the estimated PN sequence with residual carrier, it estimates and tracks the residual carrier, removes the residual carrier in the end. Theory analysis and computer simulation results show that this method can effectively realize the PN sequence estimation from the input DS signals with residual carrier in lower SNR.     

Run-time generation of partial FPGA configurations

This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The proposed approach combines partial bitstreams of coarse-grained components to produce a new partial bitstream implementing a given circuit netlist. Topological sorting of the netlist is used to determine the initial positions of individual components, whose placement is then improved by simulated annealing. Connection routing is done by a breadth-first search of the reconfigurable area based on a simplified resource model of the reconfigurable fabric. The desired partial bitstream is constructed by merging together the default bitstream of the reconfigurable area, the relocated partial bitstreams of the components, and the configurations of the switch matrices used for routing. The approach is embodied in a code library that applications can use to create new bitstreams at run-time. For the members of a set of 29 benchmarks (both synthetic and application-derived) having between five and 41 components, the complete process of bitstream generation takes between 8 s and 35 s when running on an embedded PowerPC 405 microprocessor clocked at 300 MHz.     

Register allocation for write activity minimization on non-volatile main memory for embedded systems

Non-volatile memories are good candidates for DRAM replacement as main memory in embedded systems and they have many desirable characteristics. Nevertheless, the disadvantages of non-volatile memory co-exist with its advantages. First, the lifetime of some of the non-volatile memories is limited by the number of erase operations. Second, read and write operations have asymmetric speed or power consumption in non-volatile memory. This paper focuses on the embedded systems using non-volatile memory as main memory. We propose register allocation technique with re-computation to reduce the number of store instructions. When non-volatile memory is applied as the main memory, reducing store instructions will reduce write activities on non-volatile memory. To re-compute the spills effectively during register allocation, a novel potential spill selection strategy is proposed. During this process, live range splitting is utilized to split certain long live ranges such that they are more likely to be assigned into registers. In addition, techniques for re-computation overhead reduction is proposed on systems with multiple functional units. With the proposed approach, the lifetime of non-volatile memory is extended accordingly. The experimental results demonstrate that the proposed technique can efficiently reduce the number of store instructions on systems with non-volatile memory by 33% on average.