基于射频技术的无刷同步电机励磁电流的检测

无刷同步电机的励磁系统对励磁电流的测量是制约该励磁方式发展的一大障碍。设计了一个射频系统可以用来解决同步电机的励磁电流的测量问题。该系统可以方便地检测到同步电机励磁机的整流二极管的工作状态并且可以动态地显示励磁电流，极大地方便了运行人员做出判断，而且结构简单、方便实用。     

Improved homogenization of Ni in sintered steels through the use of Cr-containing prealloyed powders

The homogenization of Ni in powder metal (PM) steel compacts is usually difficult even after high-temperature sintering at 1250°C. An earlier study by the authors demonstrated that this problem can be alleviated through the addition of 0.5 wt pct Cr in the form of stainless steel powders. To further improve the microstructure and mechanical properties of Ni-containing PM steels and to understand the mechanisms, an attempt was made in this study using the Fe-3Cr-0.5Mo prealloyed powder as the base material. The results showed that the distribution of the Ni additives was significantly improved. As a result, the tensile strength of the Fe-3Cr-0.5Mo-4Ni-0.5C compact sintered at 1250°C reached 1323 MPa. The elongation was higher than 1 pct. These sinter-hardened properties, which were attained using a slow furnace cooling rate, were comparable to those of the sinter-hardened alloys reported in the literature using accelerated cooling and were equivalent to those of the best quenched-and-tempered alloys registered in the Metal Powder Industries Federation (MPIF) standards. These improvements were attributed to the positive effect of Cr addition on alloy homogenization due to the reduction of the repelling effect between Ni and C, as was demonstrated through the thermodynamic analysis using the Thermo-Calc program.     

变频器调速装置节能浅析

1概述 近十多年来,随着电力电子技术、微电子技术及现代控制理论的发展,变频调速技术已经广泛地用于交流电动机的速度控制,其最主要的特点是具有高效率的驱动性能及良好的控制特性.它是一种高新技术电力节能装置,它通过改变（降低）电源工作频率,来降低动力设备（电机）的转速,减少设备的输出功率,达到输出功率与工作负荷的最佳匹配,实现节能目的,有效地提高了经济效益和产品质量.几乎可以说,有电动机的地方就有变频器,在一切需要进行速度控制的场合,变频器以其操作方便、体积小、控制性能高而获得广泛应用.     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

北部湾盆地福山凹陷CO2气成因探讨

北部湾盆地福山凹陷油气钻探中发现了高含CO₂气的天然气气藏。对CO₂气稳定碳同位素、伴生稀有气体氦和氩同位素进行了分析研究，结果显示，福山凹陷CO₂气稳定碳同位素偏重，(13C_CO2为-5.01～-10.08‰，绝大多数样品大于-7.0‰，为无机成因CO₂气特征；伴生稀有气体氦同位素³He/⁴He值为(4.74~5.03)×10^-6，R/Ra值为3.38～3.59；伴生稀有气体氩同位素⁴⁰Ar/³⁶Ar值为1881～2190，也显示出幔源或壳幔混合CO₂气的特征。综合判定认为，福山凹陷CO₂为壳幔混合成因。始新统流沙港组岩浆岩体分布特征与CO₂气藏分布范围基本一致，也表明幔源-岩浆可能是福山凹陷CO₂气的主要来源。与南海北部边缘盆地其它地区如珠江口盆地西部、琼东南盆地东部CO₂气成因一致，都为幔源-岩浆来源，或壳幔混合来源。     

丙烯腈装置回收塔内聚合物生成原因的分析

针对丙烯腈生产过程中回收塔内聚合物堵塞降液管造成回收塔运行周期短的问题,通过对丙烯腈回收塔内各组分分布的模拟计算,直观显示了回收塔内各组分的浓度分布,发现了回收塔的聚合段与丙烯醛的富集段相吻合的现象,初步得出了回收塔内局部聚合的原因;通过对塔内聚合物的特性分析和评判,进一步证实了“回收塔内局部聚合严重是由于在聚合段丙烯醛聚集引起”这一现象;根据模拟计算结果和实际运行经验,提出了预防聚合物堵塞降液管的措施,并进行了部分生产验证,为丙烯腈生产企业延长装置运行周期提供了理论指导。     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.