Ternary alloying study of MoSi2

Ternary alloying of MoSi₂ with adding a series of transition elements was investigated by X-ray diffraction (XRD), scanning electron microscopy, transmission electron microscopy (TEM), and energy dispersive spectroscopy (EDS). Iron, Co, Ni, Cr, V, Ti, and Nb were chosen as alloying elements according to the AB₂ structure map or the atomic size factor. The studied MoSi₂ base alloys were prepared by the arc melting process from high-purity metals. The EDS analysis showed that Fe, Co, and Ni have no solid solubility in as-cast MoSi₂, while Cr, V, Ti, and Nb exhibit limited solid solubilities, which were determined to be 1.4±0.7, 1.4±0.4, 0.4±0.1, and 0.8±0.1. Micro-structural characterization indicated that Mo-Si-M_VIII (M_VIII=Fe, Co, Ni) and Mo-Si-Cr alloys have a two-phase as-cast microstructure, i.e., MoSi₂ matrix and the second-phase FeSi₂, CoSi, NiSi₂, and CrSi₂, respectively. In as-cast Mo-Si-V, Mo-Si-Ti, and Mo-Si-Nb alloys, besides MoSi₂ and C40 phases, the third phases were observed, which have been identified to be (Mo, V)₅Si₃, TiSi₂, and (Mo, Nb)₅Si₃.     

凸轮机构基圆半径的确定方法及其分析

基圆半径的确定方法，除了用图解法和试算法外，还可用解析法和图解分析法求解。４种方法各有优缺点，设计时要根据具体情况选择。     

第三只眼看进品保健品

许多国家大多没有严格意义上的保健品概念，美国等国家将其统称为“功能食品”。我国应用“保健品”一词，旨在将其与药品和食品两大门类区分开来。美国的“保健品”发展速度和规模比较大，同时由于其先进的制造和科研技术，引领着世界功能食品的潮流。随着我国社会的发展，保健品的生产和研发也逐步赶上国际的步伐，而大量的进口保健品也已经进入寻常百姓家。     

中频反应溅射SiO2膜与直流溅射ITO膜的在线联镀

多数ITO透明导电玻璃生产线在实现SiO2膜与ITO膜在线联镀时，应用SiO2靶射频溅射沉积SiO2膜工艺和ITO靶直流溅射沉积ITO膜工艺，如果SiO2膜应用硅靶反应磁控溅射工艺，存在这种工艺是否可以与ITO靶直流溅射沉积ITO膜工艺在线联用以及如何实现联用的问题。作者对现有的生产线进行了改造设计、加工，做了大量实验、质谱分析和多项测试研究，成功地实现反应溅射SiO2膜与ITO膜在线联镀，做到SiO2镀膜室的工作状态的变化基本上不影响ITO镀膜室的工艺条件。     

用于微波/射频集成电路的一种新型低损耗介质——多孔硅及氧化多孔硅厚膜

提出在单片微波集成电路(MMIC)中用多孔硅/氧化多孔硅厚膜作微波无源器件的低损耗介质膜.研究了厚度为70μm的多孔硅/氧化多孔硅厚膜在低阻硅衬底上的形成,这层厚膜增加了衬底的电阻率,减少了微波的有效介质损耗.通过测量在低阻硅衬底上形成的氧化多孔硅厚膜上的共平面波导的微波特性,证明了在低阻硅衬底上用厚膜氧化多孔硅可以提高共平面传输线(CPW)的微波特性.     

A systematic data integration technique for mold-surface polishing processes planning

This paper presents a new MSDI (mold surface data integration) method for presenting ruled mold-surface data for CAPP applications. The method makes use of adjacency and feature-data matrices to establish a framework of feature-based data. The MSDI method enables the storage, retrieval and operations of geometries, topologies, and machining information of a given ruled mold surface. The matrices of adjacency and feature-data effectively represent the relations. Boolean algebra and group technology (GT) methods are introduced to generate the desired process plans. A sample mold made of ruled surfaces is made and used to show the effectiveness of the proposed data representation and the integrated mold surface processing method. A compact computer program is implemented to enhance the speed and accuracy of the MSDI method. The numerical results indicate that the mold surface decomposition and integration procedure presented in this paper are systematic and effective. The paper provides a novel modular mold surface modeling tool and procedure that can be further extended to accommodate more features appearing in complicated ruled mold surfaces.     

Design and analysis of low-power cache using two-level filter scheme

Power consumption is an increasingly pressing problem in modern processor design. Since the on-chip caches usually consume a significant amount of power, it is one of the most attractive targets for power reduction. This paper presents a two-level filter scheme, which consists of the L1 and L2 filters, to reduce the power consumption of the on-chip cache. The main idea of the proposed scheme is motivated by the substantial unnecessary activities in conventional cache architecture. We use a single block buffer as the L1 filter to eliminate the unnecessary cache accesses. In the L2 filter, we then propose a new sentry-tag architecture to further filter out the unnecessary way activities in case of the L1 filter miss. We use SimpleScalar to simulate the SPEC2000 benchmarks and perform the HSPICE simulations to evaluate the proposed architecture. Experimental results show that the two-level filter scheme can effectively reduce the cache power consumption by eliminating most unnecessary cache activities, while the compromise of system performance is negligible. Compared to a conventional instruction cache (32 kB, two-way) implemented with only the L1 filter, the use of a two-level filter can result in roughly 30% reduction in total cache power consumption. Similarly, compared to a conventional data cache (32 kB, four-way) implemented with only the L1 filter, the total cache power reduction is approximately 46%.     

Parameter evaluation in automated digital deep-level transientspectroscopy (DLTS)

A method of directly evaluating the activation energy ΔE, capture cross section σ, and density N_T, of deep-level traps from the pulsed reverse bias capacitance transient is described. The main advantages of this technique are that it requires only a single temperature scan, and it can resolve nonexponential transients due to closely-spaced energy levels. The test samples used for this paper consisted of Schottky diodes fabricated on nonirradiated and 1-MeV electron-irradiated n-type VPE (vapor-phase epitaxy) GaAs wafers. The well known EL2 trap was identified with ΔE of 0.81 eV, and σ _n of 1.0×10^-13 cm² for the nonirradiated sample. These values were found to be in good agreement with published data using established, conventional DLTS techniques. For the irradiated samples a nonexponential capacitance transient was found in the EL2 range of temperatures. The discussed technique was able to resolve two closely spaced deep levels lying at E_c-0.81 eV and E_c-0.84 eV, and with capture cross sections of 1.5×10^-13 cm² and 2.5×10^-12 cm², respectively