深圳市福田水闸改造设计

文章介绍了深圳市福田水闸改造中自动化设计情况,通过闸门结构、启闭机的选型、电气设备控制,将其由防洪意义的“挡潮闸”转变为截污意义的“挡潮闸”,从而实现了工程管理的现代化。     

特低渗透油气藏成岩储集相的定量评价方法

针对陕北斜坡东部特低渗透储层受沉积作用和成岩作用两大因素控制的特点，利用灰色系统理论对成岩储集相进行了研究。分析了成岩作用综合效应及其相应的视压实率、视肢结率、视微孔率、成岩综合系数等定量指标和岩心分析数据，建立了成岩储集相综合评价参数、指标和分析方法。通过在安塞油田低孔隙度特低渗透长6。油藏储层的实际应用，对目的层段开展了Ⅰ，Ⅱ，Ⅲ和Ⅳ类成岩储集相的定量评价和油气富集描述，有机地集成和综合了多种信息，实现了成岩储集相对沉积学、岩石学和成岩作用等特征的综合表征，并划分出有利成岩储集相区域，为指导油田有利含油区块的筛选和开发决策提供了重要依据。     

A Golden Section approach to optimization of automotive friction materials

A Golden Section approach combined with relational grade analysis is proposed as an experimental design tool helpful in the development of new automotive friction materials. Golden Section was used to design the volume fraction of the components systematically. The changes in friction performance (friction coefficient and wear) measured using Friction Assessment and Screening Test (FAST) can be correlated with component variations by use of relational grade analysis. This approach was utilized to optimize a non-metallic friction material containing seven ingredients including two fibers (aramid and slag fiber), four fillers (Al₂O₃, BaSO₄, graphite and nitrile rubber) and one binder (benzoxazine). The volume fraction of seven components was varied simultaneously in order to optimize the parameters of friction coefficient and wear with a minimum number of tests. Three phases were performed to find the optimal proportion of the components. The optimized friction performance was obtained after doing 19 formulation experiments.     

A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme

This paper describes a 32-KB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual-V/sub TH/ CMOS technology. The local bitline uses a leakage-tolerant self reverse-bias (SRB) scheme with nMOS source-follower pullup access transistors, while preserving robust full-swing operation. Gate-source underdrive of -220 mV on the bitline read-select transistors is established without external bias voltages or gate-oxide overstress. Device-level measurements in the 130-nm technology show 72/spl times/ bitline active leakage reduction, enabling low-V/sub TH/ usage, 40% bitline keeper downsizing, and 16 bitcells/bitline. 11% faster read delay and 2/spl times/ higher dc noise robustness are achieved compared with high-performance dual-V/sub TH/ bitline scheme. Sustained performance and robustness benefits of the SRB technique against conventional dynamic bitline with scaling to 100- and 70-nm technology is also presented.     

TD-SCDMA技术及市场分析

TD-SCDMA技术优势 2000年5月,在土耳其伊斯坦布尔召开的国际电联大会上,TD-SCDMA被国际电联接纳为第三代移动通信系统标准之一,这标志着中国在移动通信技术领域已经进入世界先进行列.     

Hydrogenated amorphous silicon thin-film transistor arrays fabricated by digital lithography

A jet-printed digital-lithographic method, in place of conventional photolithography, was used to fabricate 64 /spl times/ 64 pixel (300 /spl mu/m pitch) matrix addressing thin-film transistor (TFT) arrays. The average hydrogenated amorphous silicon TFT device within an array had a threshold voltage of /spl sim/3.5 V, carrier mobility of 0.7 cm/sup 2//V/spl middot/s, subthreshold slope of 0.76 V/decade, and an on/off ratio of 10/sup 8/.     

A NEW LARGE CAVITATION CHANNEL IN CHINA SHIP SCIENTIFIC RESEARCH CENTER

1 .　INTRODUCTIONIntherecentdecades ,itisrealizedthatitisquitenecessarytocarryouttestsathighReynoldsnumberwithalowbackgroundnoiselevelinordertomeetmoreandmoreurgentneedsofmodernnavyandmaritimeindustry .Anewlargecavita tionchannelisdevelopedinCSSRCfortestingcompletehull/ propulsor/appendagesarrange ments[1] .Itrepresentsoneofthelatestintechno logicallyadvancedlargecavitationtestfacilities.Inthefollowingsections ,thefeaturesandthefirsttestresultsofthechannelwillbedescribed .2 .　DICRIP…