SiOx:Er薄膜材料光致发光特性的研究

采用射频磁控反应溅射技术,以Er2O3和Si为靶材,制备了SiOx:Er薄膜材料,在不同温度和不同时间下进行退火处理,室温下测量了样品的光致发光(PL)谱,观察到Er3+在1 530,1 542和1 555 nm处波长的发光,发现退火能明显增强Er3+的发光.研究了退火温度和时间对SiOx:Er薄膜光致发光的影响,发现Er2O3与Si面积比为1∶1时,1 100℃下20 min退火为样品的最佳退火条件.采用XRD和材料光吸收测试对样品结构和光学性质进行了研究,得到样品中Si晶粒大小为1.6 nm,样品的光学带隙为1.56 eV.对3种不同Er2O3与Si面积比的SiOx:Er薄膜材料进行研究,得到Er2O3与Si面积比为1∶3为样品的最佳配比,对薄膜材料发光现象进行了探讨.     

基于XML自动评阅系统的设计与实现

本文针对面向大面积学生实验操作考试和阅卷的困难,提出了基于XML形式对试题知识考点进行描述的设计思想,通过对操作考试中记录的实验参数、实验状态和实验结果的XML数据进行解析评判,实现对学生实验操作考核自动评阅。在面向大面积学生的实验操作考试中,节省了大量人力、物力,具有很强的实用性。本文以大学物理仿真实验考试系统为例,实现了基于XML描述方案的实验考核自动评阅系统。     

双频雷达测高技术研究

该文针对双频雷达的测高问题,研究了基于相位干涉原理的双频雷达测高方法。文中给出了相位干涉测角的基本原理,并针对该方法在双频雷达测高应用中存在的相位模糊问题进行了分析,在此基础上,给出了基于中国余数定理的双波段相位差解模糊处理方法,解决了双频雷达相位干涉测高法的相位模糊问题。最后对双频雷达相位干涉测高法的测高精度进行了分析。仿真分析,验证了算法的可行性。     

Ultra high-speed InP/InGaAs SHBTs with ft and fmax of 185 GHz

An InP/InGaAs single heterojunction bipolar transistor (SHBT) with high maximum oscillation frequency (f_max) and high cutoff frequency (f_t) is reported. Efforts have been made to maximize f_max and f_t simultaneously including optimizing the epitaxial structure, base–collector mesa over-etching and base surface preparation. The measured f_t and f_max both reached 185 GHz with an emitter size of 1 × 20 μ m², which is the highest f_max for SHBTs in mainland China. The device is suitable for ultra-high speed digital circuits and low power analog applications.     

一个1.2伏CMOS0.13微米工艺19.2毫瓦10位30兆采样率流水线模数转换器

A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented. For the sake of lower power and area, the pipelined stages are scaled in current and area, and op amps are shared between the successive stages. The ADC is realized in the 0.13-μ m 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range, poor analog characteristic devices, the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference. Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio, 67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal. The FoM is 0.33 pJ/step. The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB, respectively. The ADC core area is 0.94 mm².     

新的V-BLAST系统次优天线选择

该文提出新的基于ZF SIC检测的V-BLAST系统次优天线选择准则：最小化信道矩阵伪逆的最大行范数。基于贪婪选择思想,发射天线选择采用使得该范数增加最小的递增选择策略,接收天线选择采用使得该范数减少最大的递减选择策略。仿真表明所提出的新准则明显优于已有的最大第1检测层后处理信噪比准则,且相应的快速选择算法可以获得最优的基于最大最小准则的全搜索选择的大部分分集增益,而复杂度很低。     

Thermal stability of Hfl'aON films prepared by physical vapor deposition

We investigate the thermal stability of HfTaON films prepared by physical vapor deposition using high resolution transmission electronic microscope (HRTEM) and X-ray photoelectron spectroscopy (XPS). The results indicate that the magnetron-sputtered HtTaON films on Si substrate are not stable during the post-deposition an-healing (PDA). HfTaON will react with Si and form the interfacial layer at the interface between HfTaON and Si substrate. Hf-N bonds are not stale at high temperature and easily replaced by oxygen, resulting in significant loss of nitrogen from the bulk film. SiO2 buffer layer introduction at the interface of HfTaON and Si substrate may effec-tively suppress their reaction and control the formation of thicker interfacial layer. But SiO2 is a low k gate dielectric and too thicker SiO2 buffer layer will increase the gate dielectric's equivalent oxide thickness. SiON prepared by oxidation of N-implanted Si substrate has thinner physical thickness than SiO2 and is helpful to reduce the gate dielectric's equivalent oxide thickness.     

Impacts of additive uniaxial strain on hole mobility in bulk Si and strained-Si p-MOSFETs

Hole mobility changes under uniaxial and combinational stress in different directions are characterized and analyzed by applying additive mechanical uniaxial stress to bulk Si and SiGe-virtual-substrate-induced strained-Si (s-Si) p-MOSFETs (metal-oxide-semiconductor field-effect transistors) along <110> and <100> channel directions. In bulk Si, a mobility enhancement peak is found under uniaxial compressive strain in the low vertical field. The combination of (100) direction uniaxial tensile strain and substrate-induced biaxial tensile strain provides a higher mobility relative to the (110) direction, opposite to the situation in bulk Si. But the combinational strain experiences a gain loss at high field, which means that uniaxial compressive strain may still be a better choice. The mobility enhancement of SiGe-induced strained p-MOSFETs along the (110) direction under additive uniaxial tension is explained by the competition between biaxial and shear stress.     

Effects of silicon nitride diffusion barrier on germanium MOS capacitors with HfON gate dielectrics

MOS capacitors with hafnium oxynitride (HfON) gate dielectrics were fabricated on Ge and Si substrates using the RF reactive magnetron sputtering method. A large amount of fixed charges and interface traps exist at the Ge/HfON interface. HRTEM and XPS analyses show that Ge oxides were grown and diffused into HfON after post metal annealing. A Si nitride interfacial layer was inserted between Ge and HfON as diffusion barrier. Using this method, well behaved capacitance-voltage and current-voltage characteristics were obtained. Finally hystereses are compared under different process conditions and possible causes are discussed.     

A wafer-level 3D packaging structure with Benzocyclobutene as a dielectric for multichip module fabrication

A new wafer-level 3D packaging structure with Benzocyclobutene (BCB) as interlayer dielectrics (ELDs) for multichip module fabrication is proposed for application in the Ku-band wave. The packaging structure consists of two layers of BCB films and three layers of metallized films, in which the monolithic microwave IC (MMIC), thin film resistors, striplines and microstrip lines are integrated. Wet etched cavities fabricated on the silicon substrate are used for mounting active and passive components. BCB layers cover the components and serve as ILDs for interconnections. Gold bumps are used as electric interconnections between different layers, which eliminates the need to prepare vias by costly dry etching and deposition processes. In order to get high-quality BCB films for the subsequent chemical mechanical planarization (CMP) and multilayer metallization processes, the BCB curing profile is optimized and the roughness of the BCB film after the CMP process is kept lower than 10 nm. The thermal, mechanical and electrical properties of the packaging structure are investigated. The thermal resistance can be controlled below 2 ℃/W. The average shear strength of the gold bumps on the BCB surface is around 70 N/mm~2. The performances of MMIC and interconnection structure at high frequencies are optimized and tested. The 5 -parameters curves of the packaged MMIC shift slightly showing perfect transmission character. The insertion loss change after the packaging process is less than 1 dB range at the operating frequency and the return loss is less than -8 dB from 10 to 15 GHz.