基于参数依赖关系检查的测试用例空间约简方法

针对待测功能函数各参数间存在的控制或数据依赖关系,提出了一种利用符号执行约简测试用例空间的算法.具体内容包括:给出了基于控制流图的程序参数依赖关系定义;在此基础上,根据输入参数变量在程序执行时的信息流,提出了一种参数依赖关系的动态分析算法;将该方法应用于可信软件栈的功能测试中.实验结果表明:该方法在约简测试用例空间上具有较强的实用性,同时不会降低测试原有的检错能力.     

Down-scaling LUCC based on the histo-variogram

In remote sensing applications, accurate extraction of land type area after classification is very important. But for images of land use/cover change (LUCC) obtained from the special spatial resolution remote sensing data, it will be of great significance to obtain the land type area information with higher resolution by making use of spatial distribution characteristcs information of the land type itself first and further scaling-down in a given scale threshold on the basis of the existing spatial resolution data. An explicit expression of the relationship between the measurement scale, global fractal dimension and the land type area corresponding to different measurement scales is obtained on the research basis of the authors’ histo-variogram using the standardized area index (SAI). A good attempt has been made to obtain the land type area information with higher resolution by merely using the spatial distribution characteristcs information of the land type in the image itself and further scaling-down in a given scale threshold on the basis of the existing spatial resolution data. Supported by the National Natural Science Foundation of China (Grant No. 40601068), the National Basic Research Program of China (“973” Project) (Grant No. 2007CB714402) and the Key Science and Technology R&D Program of Qinghai Province (Grant No. 2006-6-160-01)     

UML用例图在软件工程中的步骤设计研究

用例图作为uml的一种建模图形广泛应用在面向对象软件系统开发过程中,首先,界定了用例图在软件开发周期模型中的应用,接着,以“中国证券交易系统”中“上市公司股票发行”子用例图设计为例,详细描述了功能用例子图的绘制过程,然后,对整个软件系统的用例图的绘制过程进行了描述,给出了待开发系统的整体用例图.     

SPG-Suite：面向伪周期时间序列的预测方法

伪周期时间序列是一种广泛存在的数据形式,它具有伪周期性、非平稳性和特征值等特征。对这类时间序列进行预测,具有很强的研究和应用意义。然而,目前的相关研究对伪周期时间序列的关注度不足,一些已有的时间序列预测方法在应用到伪周期时间序列上时,会造成误差的累积,使得预测效果很差。为了解决这些问题,总结了伪周期时间序列的特征,并提出了SPG-Suite预测方法,很好地解决了传统方法无法解决的问题。最后,在真实的数据集上进行了实验,并与传统方法进行了对比,实验结果表明,SPG-Suite方法在预测精度上具有明显的优势,并具有较强的可扩展性。     

Implementing optimized pairings with elliptic nets

In this paper,we use elliptic nets to implement the optimized Ate pairings and optimal pairings on the Barreto-Naehrig curves with embedding degree 12.In order to do the arithmetic of elliptic curves over finite fields with elliptic nets,we first give some basic properties of elliptic nets associated to elliptic curves over finite fields and the expression of Miller function in terms of elliptic nets.Then we give formulae to compute some optimized pairings with elliptic nets,which is a new method to implement pairings.This method with elliptic nets has time complexity comparable to Miller’s algorithm and it can be optimized.     

Survivability-oriented optimal node density for randomly deployed wireless sensor networks

The survivability is usually critical for wireless sensor networks,which are often deployed in the unattended harsh environment.Lots of technical schemes to improve the survivability depend on the redundant resources of the sensor networks.The amount of resources is usually determined by the node density during the deployment phase.For the random deployment and random node failures,the quantitative relation between the survivability and the node density is studied.Based on the conditional survivability,the node density to meet the required survivability level is presented.Finally,the survivability for unpredictable failures and the optimal node density to maximize the price–performance ratio are also discussed.     

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

With the technology scaling down, low power dissipation has become one of the research focuses in the field of integrated circuit design. Various types of adiabatic logics have been invented for low-power applications. However, the expanding leakage current degrades the performance of conventional adiabatic logics. In this article, a novel improved complementary pass-transistor adiabatic logic （ICPAL） based on fin-type field- effect transistor （FinFET） devices with ultra-low power dissipation has been presented. The proposed ICPAL takes full advantage of different FinFET operating modes, that is, shorted-gate mode, independent-gate mode, and low-power mode, to make a tremendous reduction in power dissipation. For explication and verification, the power dissipation of different ICPAL standard cells has been investigated and compared with other types of adiabatic circuits based on FinFETs. The results show that the ICPAL circuits have ultra-low power dissipation in a wide range of clock frequencies（30-800 MHz） under the condition of similar number of transistors, and the average reduction in power dissipation is about 23.1%, 75.0%, and 50.0% relative to 2N-2N2P, improved pass- transistor adiabatic logic, and complimentary pass-transistor adiabatic logic, respectively. Furthermore, ICPAL supports a better pre-evaluation of system power dissipation in VLSI design and has an intrinsic characteristic for the resistance to some types of side channel attacks.     

Lattice-based key exchange on small integer solution problem

In this paper, we propose a new hard problem, called bilateral inhomogeneous small integer solution （Bi-ISIS）, which can be seen as an extension of the small integer solution problem on lattices. The main idea is that, instead of choosing a rectangle matrix, we choose a square matrix with small rank to generate Bi-ISIS problem without affecting the hardness of the underlying SIS problem. Based on this new problem, we present two new hardness problems： computational Bi-ISIS and decisional problems. As a direct application of these problems, we construct a new lattice-based key exchange （KE） protocol, which is analogous to the classic Diffie- Hellman KE protocol. We prove the security of this protocol and show that it provides better security in case of worst-case hardness of lattice problems, relatively efficient implementations, and great simplicity.     

A novel low-noise high-linearity CMOS transmitter for mobile UHF RFID reader

A novel CMOS transmitter with low TX noise and high linearity is implemented in a 0.18μm 1P6M standard CMOS process for Mobile UHF RFID reader.Adopting double-sideband amplitude-shift-keying(DSBASK)as the only modulation is supported,this transmitter has very low power consumption.A novel analog baseband circuit is proposed to reduce the transmitter noise.With a G′′m–cancellation technology,a highly linear up-conversion active mixer and a power amplifier driver are designed.The transmitter has a measured output1 dB compression point of 13.4 dBm.Occupying a silicon area of about 1 mm2and consuming 144 mW from a1.8 V voltage supply,the transmitter makes the Mobile UHF RFID reader communicate with a transponder in a distance of 1 m conveniently.     

A 6-bit 2 GS/s ADC in 65 nm CMOS

A 6-bit 2 GS/s ADC was implemented using a 65 nm digital CMOS technology.The design is based on a single-channel flash ADC architecture,and utilizes interpolating and averaging techniques.A two-stage CML-CMOS high-speed hybrid comparator is designed for optimal speed and power performance.The total power consumption of the converter is 52 mW and the area is 0.24 mm2.The ADC achieves 42.5 dB SFDR and5.2 bit ENOB at input frequency of 123 MHz,and at Nyquist frequency 37.67 dB SFDR and 4.9 bit ENOB.