Lattice Boltzmann method study of effect three dimensional stacking-chip package layout on micro-void formation during encapsulation process

The current study applied the lattice Boltzmann method to examine the effects of stacking chips layout to the micro-void formation in three-dimensional (3D) packaging. Three-dimensional 19-velocities commonly known as D3Q19 scheme is utilized in this study. Three different cases, which are different in layout design, are examined. For code verification purpose, an experimental work is also presented to compare the flow front results between numerical and experimental at different filling percentage. The numerical predictions compared well with the experimental results. Minor differences are observed in their flow front profile. The numerical findings identified the predicted locations of micro-void formation during the encapsulation process. The entrapment of micro-void was visualized clearly in the simulation because of the unbalanced molecular force at the interface during encapsulation. Knit lines were also identified at the interface between the flows that occurred in the encapsulation. Different layout of stacking flip-chips package have influence the micro-void in the package, which tended to form at the stacking chips region. The results show that the lattice Boltzmann method has a good performance in the IC encapsulation simulation.     

Effect of deposition temperature on structural,optical properties and configuration of CdSe nanocrystalline thin films deposited by chemical bath deposition

CdSe nanoparticle thin films were deposited on glass substrates by the chemical bath deposition (CBD) method at low deposition temperature ranging from room temperature up to 50 °C while the pH of the bath was kept constant at 12.1. The structural and morphological variation were investigated by X-ray diffraction (XRD) and scanning electron microscopy (SEM) technique. The energy band gap and optical properties were characterized by the absorbance spectra. Rutherford backscattering spectroscopy (RBS) analysis reveals the excess of Cd rather than Se in depth profile along the thin film thickness. The prepared CdSe nanoparticles have cubic structure and by increasing the temperature the deposited films become continues, homogeneous and tightly adherent. The results also revealed that by increasing the deposition temperature from room temperature up to 50 °C, the band gap decreases from 3.52 eV up to 1.84 eV.     

Hole trapping in E-beam irradiated SiO2 films

Low energy (25 kV) electron beam irradiation of MOS capacitors is shown to produce neutral hole traps in thin ‘radiation hardened’ SiO₂ films. These traps are found in an uncharged state after irradiation and are populated by passing a small hole current, generated by avalanche breakdown of then-type silicon substrate, through the oxide. From the time dependence of the observed trapping, a capture cross-section between 1 × 10∼⁻¹³ and 1 × 10⁻¹⁴ cm² is deduced. The trap density is found to depend on the annealing conditions and incident electron beam dosage. The density of traps increases with incident electron beam exposure. Once introduced into the oxide by the radiation the traps can be removed by thermal anneals at temperatures above 500° C. Parallels between electron and hole trapping on these neutral centers are strong evidence for an amphoteric uncharged trap generated by ionizing radiation.     

High performance AlyGa1−yAs-GaAs-lrxGa1−xAs quantum well lasers defined by silicon-oxygen impurity-induced layer disordering

In these experiments impurity-induced layer disordering (IILD) utilizing chemical reduction of SiO₂ by Al (from Al_0.8Ga_0.2As) is employed to generate Si and O to effect layer disordering. The SiO₂-Al_0.8Ga_0.2As reaction is studied with respect to annealing ambient. By controlling the extent of disordering via As₄ overpressure, closely spaced (∼1μm) Si-O IILD buried heterostructure lasers can be optically coupled or uncoupled. Direct observation of O incorporation into the buried layers is shown using secondary ion mass spectroscopy (SIMS). The thermal stability of separate-confinement Al_yGa_1−yAs-GaAs-In_xGa_1−xAs quantum well heterostructure (QWH) laser crystals is investigated using SIMS, transmission electron microscopy (TEM), and photoluminescence (PL) measurements. The data show that the thermal stability of a strained-layer In_0.1Ga_0.9As quantum well (QW) is strongly dependent upon: (1) the layer thickness and heterointerfaces of the Al_yGa_1−yAs-GaAs waveguide layers located directly above and below the QW, (2) the type of surface encapsulant employed, and (3) the annealing ambient. Narrow single-stripe (<2μm) lasers fabricated via Si-O diffusion and layer disordering exhibit low threshold currents (I_th ∼ 4 mA) and differential quantum efficiencies,η, of 22% per facet under continuous (cw) room-temperature operation.     

Photoluminescence characterization of the effects of rapid thermal annealing on AlGaAs/GaAs modulation-doped quantum wells

In this study, we describe the effects of rapid thermal annealing on the electrical and optical properties of modulation-doped quantum wells (MDQWs). The sheet carrier concentration in MDQW structures which have been annealed in contact with a piece of GaAs tends to decrease with increasing annealing time due to Si auto-compensation in the doped AlGaAs regions. The high energy cut-off point of 4.2 K PL spectra, which occurs at the Fermi energy, and the 77 K PL linewidth are accurate measures of sheet carrier density. These two parameters track variations in carrier density produced by annealing. Photoluminescence spectra also provide additional insight into annealing-induced changes such as Si migration, which causes a degradation in the mobility of the two-dimensional electron gas.     

Multilevel metal interconnection utilizing CVD tungsten and liftoff processing

Interconnections between semiconductor devices in integrated circuits continue to present difficult problems in the tradeoffs between RC time constants, production worthiness, reliability, structural complexity, and compactibility for any single technology. A process and structure has been demonstrated for integrated circuit interconnections which uses a conformai tungsten layer deposited by chemical vapor deposition to provide step coverage into via holes of variable height. The film is then patterned with a via interconnect pattern designed for liftoff processing, layers of chromium copper and chromium are then depositedinsitu on the wafers by way of evaporation. The undesired material is lifted off in a solvent process and the resulting metal pattern is used as the mask for the reactive ion etching of CVD tungsten. This combination of materials and process allows for high conductivity reliable interconnections with negligable step coverage problems. Processing and test information will be presented in the paper.     

基于数字电路设计直接比较型准四位ADC的仿真研究

为入门探索实现全数字化A/D转换器的集成设计方案,逐步改造4位简易ADC电路,使之成为基于门电路和触发器的设计范例。技术要点包括(1)量化编码基于CMOS非门阈值及其移动,(2)阈值移动基于非门组合传输门(替代电阻),(3)取样保持基于边沿D触发器,(4)ADC元架构业经搭建LSI电路验证成功。研究结论是Hspice仿真成功的该Flash型准4位ADC适用于低频段生物医学信号处理SoC的研制。     

Avalanche photodiode with sectional InGaAsP/InP charge layer

An InGaAs/InP avalanche photodiode (APD) with a sectional InGaAsP/InP charge layer at the heterointerface between the InGaAs absorption and InP multiplication region has been designed, fabricated and tested. We demonstrate a new APD structure that utilizes the sectional 140 nm thin charge layer and a 500 nm thin multiplication layer. The band diagram, electrical field distribution and current-voltage (I-V) characteristics up to punch-through voltage have been simulated. The fabricated mesa structure photodiode shows responsivity 0.9 A/W at 1310 nm at 20 V and avalanche gain up to 10 near breakdown voltage 36 V. The measured results revealed that the sectional charge layer could be used for control of the electric field profile in the APD structure.     

Annealing effects on physical properties of doped CdTe thin films for photovoltaic applications

Polycrystalline Cadmium Telluride (CdTe) thin films were prepared on glass substrates by thermal evaporation at the chamber ambient temperature and then annealed for an hour in vacuum ~1×10⁻⁵ mbar at 400 °C. These annealed thin films were doped with copper (Cu) via ion exchange by immersing these films in Cu (NO₃)₂ solution (1 g/1000 ml) for 20 min. Further these films were again annealed at different temperatures for better diffusion of dopant species. The physical properties of an as doped sample and samples annealed at different temperatures after doping were determined by using energy dispersive x-ray analysis (EDX), x-ray diffraction (XRD), Raman spectroscopy, transmission spectra analysis, photoconductivity response and hot probe for conductivity type. The optical band gap of these thermally evaporated Cu doped CdTe thin films was determined from the transmission spectra and was found to be in the range 1.42–1.75 eV. The direct energy band gap was found annealing temperatures dependent. The absorption coefficient was >10⁴ cm⁻¹ for incident photons having energy greater than the band gap energy. Optical density was observed also dependent on postdoping annealing temperature. All samples were found having p-type conductivity. These films are strong potential candidates for photovoltaic applications like solar cells.     

Direct and quantitative understanding of the non-Ohmic contact resistance in organic and oxide thin-film transistors

We explore the device physics of thin film transistors (TFTs) with non-Ohmic contacts and develop a simple and fast method for evaluating the contact properties TFTs through output characteristics. Using one single output scan, the quantitative relationship between contact resistances and drain voltage were evaluated, revealing the property of interfacial injection at non-Ohmic contacts. This is demonstrated and validated in both TFT simulations and experiments employing inorganic and organic TFTs. The approach can be applied to general TFTs with arbitrary materials and configurations conveniently and enables faster and improved understanding of TFT operation and device physics.