High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

Fast handoff with reducing waste rate approach for wireless resources management in UMTS mobile networks

3G Wideband CDMA systems adopt the Orthogonal Variable Spreading Factor code tree as the channelization codes management for achieving high data rate transmission in personal multimedia communications. It assigns a single channelization code for each accepted connection. Nevertheless, it wastes the system capacity when the required rate is not powers of two of the basic rate. One good solution is to assign multiple codes for each accepted connection but it causes two inevitable drawbacks: long handoff delay and new call setup delay due to high complexity of processing with multiple channelization codes, and high cost of using more number of rake combiners. Especially, long handoff delay may result in more call dropping probability and higher Grade of Service, which will degrade significantly the utilization and revenue of the 3G cellular systems. Therefore, we propose herein an adaptive efficient codes determination algorithm based on the Markov Decision Process analysis approach to reduce the waste rate and reassignments significantly while providing fast handoff. Numerical results demonstrate that the proposed approach yields several advantages, including the lowest GOS, the least waste rate, and the least number of reassignments. Meanwhile, the optimal number of rake combiners is also analyzed in this paper. This research was supported in part by the National Science Council of Taiwan, ROC, under contract NSC-93-2213-E-324-018.     

Effective Location Based Services with Dynamic Data Management in Mobile Environments

With the proliferation of mobile computing technologies, location based services have been identified as one of the most promising target application. We classify mobile information service domains based on feature characteristics of the information sources and different patterns of mobile information access. By carefully examining the service requirements, we identify the dynamic data management problem that must be addressed for effective location based services in mobile environments. We then devise a general architecture and cost model for servicing both location independent and location dependent data. Based on the architecture and cost model, we propose a set of dynamic data management strategies that employs judicious caching, proactive server pushing and neighborhood replication to reduce service cost and improve response time under changing user mobility and access patterns. Detail behavior analysis helps us in precisely capturing when and how to apply these strategies. Simulation results suggest that different strategies are effective for different types of data in response to different patterns of movement and information access. Shiow-yang Wu is an associate professor of the Department of Computer Science and Information Engineering at National Dong Hwa University, Hualien, Taiwan, R.O.C. He received the BS and MS degrees in computer engineering from National Chiao Tung University, Hsinchu, Taiwan, ROC, and the PhD degree in computer science from the University of Texas at Austin in 1984, 1986, and 1995, respectively. His research interests include data/knowledge bases, mobile computing, distributed processing, intelligence information systems, and electronic commerce. Kun-Ta Wu was born in Taipei, Taiwan, R.O.C., in 1976. He received the B.S. degree in computer science from Soochow University, Taipei, Taiwan, R.O.C., in 1999 and the M.S. degree in computer science and information engineering from National Dong Hwa University, Hualien, Taiwan, R.O.C., in 2001. Currently, he is an Assistant Researcher in the Domestic Division at Science and Technology Information Center, National Science Council, R.O.C., as a member of Information Gathering and Analysis Group of National Information and Communication Security Taskforce. His research interests include mobile computing, wireless network and information security.     

Determination of phosphorescence lifetimes in the presence of high background signals using phase-shift measurements

Phosphorescence-based optical sensors are typically based on intensity or triplet-lifetime measurements. Lifetime determinations may be performed in the frequency-domain by exciting the luminophor with a sinusoidal modulated light source and measuring the phase shift between the excitation light and the phosphorescence emission. Modulated scattered light at the same frequency of the modulating signal must be removed in order to perform accurate measurements.A new and simple method based on phase-modulation measurements is presented to measure the triplet-lifetime of a long-lifetime phosphorescent luminophor, even if high levels of background short-lived fluorescence or scattered light are present. The method is based on the measurement of the phase shift between excitation and emission light at two different frequencies and it turned to provide reliable lifetime measurements if the background light lifetime is significantly shorter than that of the phosphorescent emission to be measured.Theoretical aspects of the proposed methodology, the design and construction of a fiber-optical measuring system and the selection of the optimal frequencies to perform the accurate lifetime measurements are discussed. Finally, the performance of the proposed measurement method has been assessed in the determination of the triplet-lifetime values of the metal chelate Al-ferron immobilized in an inorganic sol–gel support (an oxygen indicator which displays a strong fluorescence emission overlapping significantly with the measured phosphorescence emission).     

Assessing stem cell research productivity

Honour Index (HoI), a method to evaluate research performance within different research fields, was derived from the impact factor (IF). It can be used to rate and compare different categories of journals. HoI was used in this study to determine the scientific productivity of stem cell research in the Asian Four Dragons (Hong Kong, Singapore, South Korea and Taiwan) from 1981 to 2001. The methodology applied in this study represents a synthesis of universal indicator studies and bibliometric analyses of subfields at the micro-level. We discuss several comparisons, and conclude the developmental trend in stem cell research for two decades. This revised version was published online in August 2006 with corrections to the Cover Date.     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.     

Effects of genotype and treatment on the antioxidant activity of sweet potato in Taiwan

Six genotypes of sweet potato commercially available in Taiwan, including TNG57, TNG66, TNG68, TYY1, RP and WP, were used as samples in this study of the effects of steaming and kneading with pre-steaming treatments on the antioxidant components and antioxidant properties of methanolic extracts. Steam treatment increased the total phenols contents of all genotypes (2–13 times), flavonoids content of RP (1.3 times) and anthocyanins contents of RP and WP (5–6 times). Steam treatment also increased the reducing power and scavenging DPPH radical effect of sweet potato flours. For the methanolic extracts of steamed and kneaded flours, reducing powers were 0.02–1.70 at 5.0 mg ml⁻¹ and the scavenging effects on DPPH radicals were 19–92% at 2.5 mg ml⁻¹. Both showed the order of RP > WP > TYY1 and TNG66 > TNG57 and TNG68. However, the chelating effect of the six genotypes at 1.0 mg ml⁻¹ ranged from 50% to 73%. Contents of total phenols, flavonoids, and anthocyanins of sweet potato flours were significantly positively correlated with the reducing power and scavenging DPPH radical effects. After steaming and kneading treatments, RP showed the highest increase in the contents of total phenols, flavonoids and anthocyanins among the six genotypes studied.