无线发码通用遥控编码芯片的ASIC设计

提出了一种通用遥控编码芯片的设计方案,阐述了芯片功能原理,对各模块的主要电路进行了设计、分析,其中给出了一些设计巧妙的电路结构,整个设计采用全原理图输入方式,最大程度地简化了电路,最后对整个方案进行了仿真.这种通用遥控编码芯片可以完成对遥控电路发送端数字基带信号的编码.外围电路简单,大大简化了板极电路的复杂度、成本低,可靠性高.这种编码芯片可以应用在家用电器遥控、车库门控制、防盗报警系统等多种遥控场合.FPGA是一种新型的高密度大容量的PLD.整个方案在FPGA中通过了原型验证.     

片上TCAM的研究和应用

为了提高片上TCAM的摆放密度和降低功耗,基于IBM 32 nm工艺库提供的TCAM的特性和优先编码器硬核,设计出同时满足多个查找宽度的外围控制电路。相比于之前的设计和实现,该设计可以减少TCAM的块数和相关寄存器的数量,减少片上TCAM的摆放面积,降低芯片的整体功耗。该设计已经成功应用于公司第4代路由交换ASIC芯片上。     

DAB接收机的原理与实现

分析了DAB接收机的基本工作原理，介绍了使用ASIC的接收机样机，并给出了该DAB试验机的结构。     

基于ASIC均衡器的研究与设计

考虑当前的数字电视系统的发展现状,提出一种可供数字电视系统使用的均衡器设计方法.设计了一种基于ASIC的用于QAM解调信号的LMS自适应均衡器,此均衡器采用线性自适应算法中的最小均方算法(LMS),其结构由线性横向滤波器和抽头系数更新模块组成.能为数字电视系统提供可靠性和灵活性,同时也缩短了设计周期,提高其抗干扰能力和信道利用率.     

基于数字ASIC设计流程的DDS设计与实现

作为第三代频率合成技术,直接数字频率合成器具有显著的优点并得到广泛的应用。在此结合数字ASIC设计流程,利用流水线技术和函数对称性性质,设计并实现一个优化的DDS电路。从系统结构划分到自动布局布线,逐步介绍各个设计阶段的目的、使用软件及设计要点。经过分析,最终得到的DDS电路能够运行在150MHz系统时钟下,并且具有较小的面积,满足设计要求。     

Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

Lightweight authenticated encryption for embedded on-chip systems

ABSTRACT

Embedded systems are routinely deployed in critical infrastructures nowadays, therefore their security is increasingly important. This, combined with the pressing requirement of deploying massive numbers of low-cost and low-energy embedded devices, stimulates the evolution of lightweight cryptography and other green-computing security mechanisms. New crypto-primitives are being proposed that offer moderate security and produce compact implementations. In this article, we present a lightweight authenticated encryption scheme based on the integrated hardware implementation of the lightweight block cipher PRESENT and the lightweight hash function SPONGENT. The presented combination of a cipher and a hash function is appropriate for implementing authenticated encryption schemes that are commonly utilized in one-way and mutual authentication protocols. We exploit their inner structure to discover hardware elements usable by both primitives, thus reducing the circuit’s size. The integrated versions demonstrate a 27% reduction in hardware area compared to the simple combination of the two primitives. The resulting solution is ported on a field-programmable gate array (FPGA) and a complete security application with input/output from a universal asynchronous receiver/transmitter (UART) gate is created. In comparison with similar implementations in hardware and software, the proposed scheme represents a better overall status.     

FPGA与ASIC的战场转向消费电子

FPGA等可编程器件与ASIC和NASSP的竞争一直是半导体产业的焦点之一；而目前经济危机造成行业增长受阻则使竞争更加激烈。一些FPGA厂商试图通过推出低功耗、低成本产品来进入以大批量为特点的消费市场，并弥补产业下滑所带来的缓慢增速，而也有厂商认为应该放弃持续下滑的消费市场。     

一种基于FPGA的UART电路实现

UART即通用异步收发器，传统上采用多功能的专用集成电路实现。但是在一般的使用中往往不需要完整的UART的功能，比如对于多串口的设备或需要加密通讯的场合使用专用集成电路实现的UART就不是最合适的。本设计使用Xilinx的FPGA器件，只将UART的核心功能嵌入到FPGA内部，不但实现了电路的异步通讯的主要功能，而且使电路更加紧凑、稳定、可靠。     

网络处理器--下一代网络发展的核心技术

阐述了网络处理器的概念及其产生的技术背景，并给出了网络处理器的基本结构，同时指出其优点。