排序方式: 共有83条查询结果,搜索用时 15 毫秒
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In this work, a new direct digital frequency synthesizer (DDFS) is proposed, which is based on a new two-level table-lookup
(TLTL) scheme combined with Taylor’s expansion. This method only needs a lookup-table size of total
bits, one
multiplier, one n × 3n/4-bit multiplier and two additional smaller multipliers, to generate both sine and cosine values (where n is the output precision). Compared with several notable DDFS’s, the new design has a smaller lookup-table size and higher
SFDR (Spurious Free Dynamic Range) for high-precision output cases, at comparable multiplier and adder complexities. The DDFS
is verified by FPGA and EDA tools using Synopsys Design Analyzer and UMC 0.25 μm cell library, assuming 16-bit output precision.
The designed 16-bit DDFS has a small gate count of 2,797, and a high SFDR of 110 dBc.
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利用直接数字频率合成和单片机控制技术,并综合应用宽带运放和双D/A稳幅设计,设计出能输出两路具有一定相位差的波形驱动控制系统。通过功率放大驱动超声波电动机,该驱动控制系统可以输出正弦波、方波、三角波,并且满足相位步进为1°,电压步进为0.1V,频率步进为1Hz。实验表明该驱动控制系统驱动效果好,通用性强。 相似文献
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中频全数字调制技术及其在DOCSIS协议中的应用 总被引:1,自引:0,他引:1
介绍中频全数字调制技术的原理,重点讨论设计全数字调制器的关键问题。在介绍DOCSIS协议物理层传输特性的基础上,给出基于中频全数字调制技术的DOCSIS调制器设计方案,提出该方案中几个关键问题的解决办法,并计算参数。 相似文献
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A non-linear interpolation based ROM-less Direct Digital Frequency Synthesisiser (DDFS) is more efficient than previous systems
as each current cell in a non-linear DAC is used more effectively. This was achieved by forming an analogue voltage from a
small linear DAC addressed by phase bits that are usually discarded. The analogue voltage was connected to a selected current
source in a thermometer decoded non-linear DAC to allow non-linear interpolation between the conventional, phase limited output
levels. By increasing the number of phase bits the spurious free dynamic range (SFDR) was improved without increasing the
size of the non-linear DAC. Modelling and simulation of the non-linear response of the differential switch based current cell
revealed suitable parameters. The architecture of 64 current cells used a modified thermometer decoder and three-state switch
in each current cell. Simulation and testing of 10 sample circuits demonstrated a robust DDFS with SFDR better than −60 dBc
and suitable for use in a wide range of instrumentation systems. 相似文献
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一种适用于数字视频编码器的高性能直接数字频率合成器 总被引:1,自引:1,他引:0
提出了一种适用于数字视频编码器的直接数字频率合成器 DDFS(Direct Digital Frequency Synthesizer)新结构 .通过采用相位截断噪声整形技术 ,使所需要的 ROM面积下降为传统结构的 1/ 8.同时采用了其它优化策略进一步减少了 ROM的面积 ,整个 DDFS仅需要 115 2 bit的 ROM.DDFS输出在 PAL 制式下信噪比为 6 9d B,NTSC制式下为 70 .7d B 相似文献
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基于FPGA的数字波形发生器 总被引:5,自引:0,他引:5
数字波形发生器基于FPGA设计,VHDL编程实现,集成在 1片Xilinx公司的SpartanⅡ系列XC2S10 0PQ2 0 8芯片上。核心技术是直接数字频率合成技术。芯片集成了固定分频器、正弦波合成器、三角波、矩形波与锯齿波发生器,波形选择模块和键盘控制模块,其输出的 8位数据通过D/A转换并经功率放大后即得所需波形。通过改变相位步进调节频率,可从 10Hz~ 30kHz等步进调节,最小步进 10Hz;通过改变D/A电阻网络的基准电压调幅度。系统频率范围宽,频率和幅度精度高 相似文献