整数阶电路基本定理到分数阶电路推广及分析

近几十年来,对分数阶电路的研究逐渐深入,但对其中电路定理的分析较少,因此针对分数阶电路需要进一步探究其规律,将一些经典的电路定理推广到分数阶电路中,使得在以后的分析过程中能直接使用。本文在整数阶电路定理的基础上,运用基尔霍夫定律在分数阶电路中证明了叠加定理、替代定理、等效电源定理和互易定理,并进行了应用分析。     

Integrated mathematical optimisation approach for the tower crane hook routing problem to satisfy material demand requests on-site

Optimising decisions around the location and operation of tower cranes can improve the workflow in construction projects. Traditionally, the location and allocation problems involved in tower crane operations in the literature have been solved separately from the assignment of material supply points to demand points and the scheduling of the crane’s activity sequence across supply and demand points on a construction site. To address the gap, this paper proposes a binary integer programming problem, where location of the tower crane, allocation of supply points to material-demanding regions, and routing of hook of the crane based on activity sequencing of the hook across supply and material-demanding regions on site are optimised. The novelty in this work is in the way the crane’s activity scheduling is modelled via mathematical programming, based on routing the hook movement to meet material demand, through minimising tower crane operating costs. A realistic case study is solved to assess the validity of the model. The model is contrasted with results obtained from other solving algorithms commonly adopted in the literature, along with a solution proposed by an experienced practitioner. Results indicate that all instances can be solved when compared to other meta-heuristics that fail to achieve an optimum solution. Compared to the solution proposed by the practitioner, the results of the proposed model achieve a 46% improvement in objective function value. Planners should optimise decisions related to the location of the crane, the crane’s hook movement to meet service requests, and supply points’ locations and assignment to material-demanding regions simultaneously for effective crane operations.     

磁阻旋转变压器等效电路及原边反射误差分析

磁阻式旋转变压器因其结构简单和高可靠性,在新能源汽车主驱电机系统中已有越来越多的应用。在磁阻式旋转变压器的应用中,旋转变压器一般被考虑为一个变比可变的理想变压器,然后根据解码原理,分析解码误差。但是在实际应用中,旋转变压器的励磁、正余弦信号均需通过一定电路进行处理,旋转变压器自身在电路中的实际表现也会引入解码误差,这就需要我们对旋转变压器进行精确的建模,以分析其在电路中的实际负载效应。本文首先介绍了磁阻式旋转变压器的基本原理,然后详细分析了其励磁、信号绕组的自感、互感,并使用励磁绕组、信号绕组的自感、互感导出旋转变压器的等效电路,最后在此等效电路基础上分析旋转变压器与其接入的电路共同引起的解码误差,为旋转变压器的应用电路设计提供依据。     

电路板级自动测试系统的设计及其应用

针对雷达电路板具有复杂多样以及维护困难大的特点,本文介绍了一种面向信号测试的电路板级自动测试系统的开发过程,重点描述了系统软件平台框架搭建和TPS可视化开发运行平台的设计以及具体应用。运行实践表明,测试策略和测试流程的可视化编程,极大地提高了雷达电路板的维修效率。     

A two-phase dynamic dispatching approach to semiconductor wafer testing

There have been numerous advancements and rising competition in semiconductor technologies. In light of this, the wafer test plays a more significant role in providing the most prompt yield feedback for quick process improvement. However, the wafer test shop floor is getting more complicated than ever before because of the increasing change-over rate, nonlinear wafer arrival, and preemption by urgent orders. Furthermore, the foundry wafer test is a heterogeneous production with different production cycle times and a large variety of nonidentical testers. Shop floor conditions, including work in process (WIP) pool, tester status, and work order priority, continuously change. There is a need to operate the kind of production line that simultaneously fulfills multiple objectives. Such objectives are maximum confirmed line item performance (CLIP) for normal lots, 100% CLIP for urgent lots, minimum change-over rate, and shortest cycle time. Thus, a reactive dispatching approach is proposed and expected to perform a real-time solution no matter how/what the shop floor would change. The dynamic approach is mainly triggered by two kinds of major events: one is when an urgent lot comes in, and the other is when a tester is idle. In addition, through a two-phase dispatching algorithm, lot ranking, and lot assignment methods, prioritized WIP lots and an appropriate lot assignment are suggested. A better performance measure is obtained by considering the multiple objectives the wafer test operations seek to achieve.     

基于信息支持设备的电路板元器件定位软件开发

信息支持设备是一种便携式的辅助维修设备,具有处理能力强、人机交互界面好、屏幕分辨率高的特点。在此平台上,利用C#语言,针对故障电路板有无PCB格式两种类型电路图进行了元器件定位软件开发,为进一步检查和测试提供有用方位信息,大大缩短了维修时间。     

基于证据理论数据融合的双效水印

提出一种新的基于证据理论的数据融合的双效水印算法.首先应用水印公式构造特殊的水印嵌入后条件,根据嵌入系数之间的定性分析提取鲁棒水印;利用嵌入系数之间的定量分析能提取脆弱水印,并能准确定位篡改的区域.其次在嵌入过程中还使用纠错码对水印信息进行调和,把水印重复嵌入到图像信息的不同位置,以便利用纠错码的辅助信息来估计出提取的...     

Negation-Limited Complexity of Parity and Inverters

In negation-limited complexity, one considers circuits with a limited number of NOT gates, being motivated by the gap in our understanding of monotone versus general circuit complexity, and hoping to better understand the power of NOT gates. We give improved lower bounds for the size (the number of AND/OR/NOT) of negation-limited circuits computing Parity and for the size of negation-limited inverters. An inverter is a circuit with inputs x ₁,…,x _n and outputs ¬ x ₁,…,¬ x _n . We show that: (a) for n=2 ^r ?1, circuits computing Parity with r?1 NOT gates have size at least 6n?log?₂(n+1)?O(1), and (b) for n=2 ^r ?1, inverters with r NOT gates have size at least 8n?log?₂(n+1)?O(1). We derive our bounds above by considering the minimum size of a circuit with at most r NOT gates that computes Parity for sorted inputs x ₁≥???≥x _n . For an arbitrary r, we completely determine the minimum size. It is 2n?r?2 for odd n and 2n?r?1 for even n for ?log?₂(n+1)??1≤r≤n/2, and it is ?3n/2??1 for r≥n/2. We also determine the minimum size of an inverter for sorted inputs with at most r NOT gates. It is 4n?3r for ?log?₂(n+1)?≤r≤n. In particular, the negation-limited inverter for sorted inputs due to Fischer, which is a core component in all the known constructions of negation-limited inverters, is shown to have the minimum possible size. Our fairly simple lower bound proofs use gate elimination arguments in a somewhat novel way.     

一种优化的射频IC接收电路

简要介绍射频IC系统的结构,并针对现有射频IC系统接收电路的不足,通过调整混频器增益、混频管之间距离和工作频率等方法,实现对接收电路的优化。通过仿真,证明了优化的有效性。