一种新颖的单片集成红外传感信号处理器

介绍一种新颖的单片集成红外传感信号处理器。这种处理器能与多种红外传感器匹配 ,对接收到的传感信号进行处理 ,产生控制信号 ,快速启动各类装置 ,实现自动控制。芯片设计中采用多种抗噪声和低功耗设计技术。本处理器用 1 .2μm双层多晶双层金属 N阱 CMOS工艺实现 ,芯片总面积 2 .7mm2 ,电源电压 5 V时的静态电流为 1 .2 m A,封装后样品测试结果获得设计预期的功能和性能     

用于综合PWM芯片的并行遗传算法

提出了基于遗传算法的脉冲宽度调制(PWM)芯片的自动综合方法.为保证综合结果准确实用,对电路性能的评价基于HSPICE的仿真结果,提出的并行遗传算法采用了电路划分和参数关联技术,并运用互联网实现并行计算.综合实例表明了该方法的有效性     

The ΣΔ-BIST Method Applied to Analog Filters

This paper describes the -BIST method, defined as an analog BIST circuit in the context of mixed signal systems. The test procedure is based on the reuse of existing analog circuits configured as sigma-delta modulators in the analog domain. The test procedure reuses most of existing blocks in a mixed signal system, and thus has small area overhead. Test sensitivity is very high, detecting small component deviations. Moreover, the proposed test technique can be applied to continuous or sampled time circuits, and the test procedure can be developed in the field. The paper explains the method and presents practical results to validate the proposed approach.     

Low-Power Log-Domain CMOS Filter Bank for 2-D Sound Source Localization

This paper proposes the design of a novel current-mode front-end for the extraction of localization spectral cues from two audio signals, together with test results. The front-end consists of two parallel filter banks, envelope extraction and comparison circuitry, together with an AGC loop. The extracted cues are intended to be further processed in order to determine the source azimuth and elevation. A current-mode log-domain implementation using subthreshold MOS operation is used for micropower operation while still achieving a good bandwidth and linearity. A current-mode solution is also preferred because of the ease of implementation of certain mathematical operations. The front-end splits the input signals into different frequency bands and computes monaural and interaural spectral cues from the resulting signal envelopes for each band. The front-end has been optimized to operate at a supply voltage of 1.8 V and most blocks have been designed using a differential architecture. To our knowledge, this is the first log-domain implementation of a front-end for 2-D localization cues extraction. The design has been carried out using a standard double-poly double-metal 0.8 m CMOS process with V _T = 0.8 V. The bandpass filters which form the main core of the chip exhibit a measured dynamic range of 62 dB corresponding to 1.9% THD, while the total power dissipation is 890 W.     

A Self-Calibrated Pipeline ADC with 200 MHz IF-Sampling Frontend

A 13-bit, 50-MS/s pipeline ADC with IF-sampling capability is presented. A high sampling linearity is obtained through the use of bootstrapped switches. A digital self-calibration algorithm with modified capacitor measurement scheme is employed to improve the accuracy of the first two pipeline stages. The prototype, implemented with a 0.35-m BiCMOS (SiGe) technology, shows a 76.5-dB SFDR at a 194.2-MHz signal frequency and dissipates 715 mW power from a 2.9-V supply.     

A Strategy for Rapid Mismatch Evaluation of Transient Characteristics of CMOS Analog Cells

A strategy is presented to evaluate the statistical means and standard deviations of the transient characteristics of CMOS analog cells. Based upon the Monte Carlo analysis of electrical simulations, this strategy follows a circuit-theory based approach achieving an important reduction on matrix ranges and consequently on the number of operations involved in the resolution of the circuit. The CPU time-consuming reduction is achieved also by saving information corresponding to the nominal transient analysis. We include comparative results for several CMOS cells showing the advantages of the proposed strategy.     

A High Speed, Low Voltage CMOS Offset Comparator

A high speed, low voltage offset comparator is presented. No common mode tracking circuit is used and the offset is added without compromising the high input impedance nature of the circuit. The circuit operates at 480 Mbps with 3.0–3.6 V and 1.6–2.0 V supplies and –40 to 125°C temperature range on a typical 0.5 m technology.     

快速搜寻卫星数字压缩信号

在没有专业仪器，没有明确参照物的条件下，如何快速定位接收天线，搜索到卫星信号，是电视工程技术人员经常遇到的问题，本文就此问题提出了一个新的解决办法，即利用已知卫星的位置来定位其它卫星的位置。     

Wide dynamic range parallel feedback transimpedance amplifier for 10 Gb/s optical links

This paper presents the design and implementation of a new wide dynamic range parallel feedback (PF) transimpedance amplifier (TIA) for 10 Gb/s optical links. The wide dynamic range is attributed to the novel TIA architecture employing both shunt-shunt and shunt-series feedback networks. The outstanding features of the TIA are wide dynamic range, high gain, low power consumption and design simplicity. A prototype implemented in a 0.5 μm SiGe BiCMOS technology and operating at −3.3 V power supply features an 18.4 dBm dynamic range with a BER less than 10⁻¹², an optical sensitivity of −16 dBm, optical overload of +2.4 dBm, a bandwidth of 8.27 GHz, a gain of 950 Ω and a power consumption of 189 mW. The new parallel feedback architecture offers improved overload and noise performance when compared to previously reported, state of the art, single feedback TIA designs and meets all the 10 Gigabit Ethernet and short-reach OC-192 SONET specifications. Ricardo Andres Aroca received the B.S. (Hons) degree in electrical engineering from the University of Windsor, Canada, and the M.S. degree from the University of Toronto, Canada, in 2001 and 2004, respectively. In 2000 he spent two 4 month internships with Nortel Networks in the Microelectronics Department. Mr. Aroca received the Natural Sciences and Engineering Research Counsel of Canada (NSERC) Postgraduate Scholarship award in 2002. He is currently working toward the Ph.D. degree at the University of Toronto where his research interests lie in the area of high-frequency integrated circuits for wireless and wireline communication systems. C. Andre T. Salama received the B.A.Sc. (Hons.) M.A.Sc. and Ph. D. degrees, all in Electrical Engineering, from the University of British Columbia in 1961, 1962 and 1966 respectively. From 1962 to 1963 he served as a Research Assistant at the University of California, Berkeley. From 1966 to 1967 he was employed at Bell Northern Research, Ottawa, as a Member of Scientific Staff working in the area of integrated circuit design. Since 1967 he has been on the staff of the Department of Electrical and Computer Engineering, University of Toronto where he held the J.M. Ham Chair in Microelectronics from 1987 to 1997. In 1992, he was appointed to his present position of University Professor for scholarly achievements and preeminence in the field of microelectronics. In 1989-90, he was awarded the ITAC/NSERC Research Fellowship in information technology. In 1994, he was awarded the Canada Council I.W. Killam Memorial Prize in Engineering for outstanding career contributions to the field of microelectronics. In 2000, he received the IEEE Millenium Medal. In 2003, he received the Outstanding Lifetime Achievement Award from the Canadian Semiconductor Technology Conference for seminal and outstanding contributions to semiconductor device research and promotion of Canadian University research in microelectronics. In 2004, he received the NSERC Lifetime Achievement Award of Research Excellence for outstanding and sustained contributions to the field of microelectronics and the Networks of Centres of Excellence (NCE) Recognition Award for research excellence and outstanding leadership.He was associate editor of the IEEE Transactions on Circuits and Systems in 1986–88 and a member of the International Electron Devices Meeting (IEDM) Technical Program Committeein 1980–82, 1987–89 and 1996–98. He was the chair of the Solid State Devices Subcommittee for IEDM in 1998 and was a member of the editorial board of Solid State Electronics from 1984 to 2002. He is presently a member of the editorial board of the Analog IC and Signal Processing Journal and the Technical Program Committee of the International Symposium on Power Semiconductor Devices and ICs (ISPSD) and the Technical ProgramCommittee of the International Symposium on Low Power Electronics and Design (ISLPED). He chaired the technical program committee of ISPSD in 1996 and was the general chair for the conference in 1999.Dr. Salama is the Scientific Director of Micronet, a network of centres of excellence focussing on microelectronics research and funded by the Canadian Government and Industry. He has published extensively in technical journals, is the holder of eleven patents and has served as a consultant to the semiconductor industry in Canada and the U.S. His research interests include the design and fabrication of semiconductor devices and integrated circuits with emphasis on deep submicron devices as well as circuits and systems for high speed, low power signal processing applications. Dr. Salama is a Fellow of the Institute of Electrical and Electronics Engineers, a Fellow of the Royal Society of Canada, a Fellow of the Canadian Academy of Engineering, a member of the Association of Professional Engineers of Ontario, the Electrochemical Society and the Innovation Management Association of Canada.     

切比雪夫Ⅱ型模拟高通滤波器的设计及实现

提出了一种基于反相积分器的信号流图来实现切比雪夫Ⅱ型模拟高通滤波器的方法。首先,基于归一化切比雪夫Ⅱ型模拟低通滤波器极点分布的特点,推导出归一化切比雪夫Ⅱ型模拟低通滤波器零极点和转移函数的公式,得到归一化切比雪夫Ⅱ型模拟低通滤波器设计的步骤;然后,基于频率变换与逆变换,提出一种利用归一化切比雪夫Ⅱ型模拟低通滤波器来设计切比雪夫Ⅱ型模拟高通滤波器的方法;最后,给出了利用归一化切比雪夫Ⅱ型模拟低通滤波器来设计切比雪夫Ⅱ型模拟高通滤波器的实例及其实现电路。