Generation of Technology-Independent Retargetable Analog Blocks

This paper introduces a complete methodology for retargeting of analog cells to different sets of specifications. This methodology is technology-independent, thus allowing the migration, from one technology to another, of the circuit under retargeting. Careful integration of the device sizing and layout generation tasks via the incorporation of layout constraints during the sizing process allows to generate fully functional designs in a few minutes. The methodology is illustrated via the retargeting of a fully-differential Miller-compensated two-stage operational amplifier for a new set of specifications and two different technological processes.An erratum to this article can be found at     

Low-Power Adaptive Biased Integrated Amplifiers

In this paper the author will present the working principle and the applications of a novel adaptive biasing topology, designed to decrease the stand-by power dissipation without affecting the transient performance of low-power amplifiers. The proposed circuit, whose principle and circuit topology can be implemented both in CMOS and in bipolar standard technologies, gives a biasing current whose value depends on the applied input differential voltage and can be set according to the requested transient performance constraints. The adaptive architecture can be utilized in the design of high-efficient low-power operational amplifiers, for the biasing of both the input stage (where the input source current is dynamically increased) and the output stage (where the output current can be controlled and limited). These amplifiers show a very good behaviour, evaluated in terms of two efficiency factors, if compared with those of other adaptive solutions and class-AB topologies, proposed in the literature. Simulation results and also measurements on a chip prototype, fabricated in a standard CMOS technology, are finally presented.     

基于双积分模拟重构大动态范围CIS系统研究

提出一种采用列共用模拟重构电路和双积分三采样工作时序的CMOS图像传感器(CIS)系统架构,可实现光电响应曲线压缩和像素固定模式噪声(FPN)消除,提高传感器动态范围到83 dB,使成像质量提高.该结构具有与单采样相同的像素阵列,仅增加很小的处理电路.改进的工作时序优化了长积分、短积分和信号处理的时序分配.系统控制由FPGA实现.功能和数模混合仿真验证表明,方案是可行的.     

基于ADS1606的高速、高精度ADC设计

ADS1606是典型的高性能模/数转换器.详细介绍了ADS1606的主要特性、数字部分控制、模拟输入方式选择、参考电压、电源特性、PCB设计要点以及多种控制结构的测试和分析等.同时,利用设计和测试ADS1606的过程,提出一些高性能模/数转换系统的设计经验.     

一种低温漂BiCMOS带隙基准电压源的设计

文章介绍了一种低温漂的BiCMOS带隙基准电压源.基于特许半导体(Chartered)0.35 μm BiCMOS工艺,采用Brokaw带隙基准电压源结构,通过一级温度补偿技术,设计得到了一种在-40℃到 85℃的温度变化范围内温度系数为15.2×10-6/℃,输出电压为2.5 V±0.002 V的带隙基准电压源电路.±20%的电源电压变化情况下,输出电压变化为2.2 mV,电源电压抑制比为60 dB.5 V电源电压下功耗为1.19 mW.具有良好的电源抑制能力.     

一种专业音频立体声相位测量仪的设计

根据广播电台和录音棚的相位检测需求,利用模拟乘法器的鉴相功能,设计出一种专业音频立体声相位测量仪,有效避免了音频节目生产过程中的反相问题.     

群时延内均衡的模拟滤波器优化设计

为解决滤波器幅频特性算术对称性和通带内群时延波动之间的矛盾,提出了一种滤波器群时延内均衡优化设计方法,即在网络综合法设计的滤波器电路基础上,将电路与时延均衡器直接耦合,用最小二乘法使群时延特性逼近一个常数,然后利用无约束优化算法对整个电路进行优化来降低通带内群时延波动.仿真结果表明,该方法不但能使滤波器幅频特性算术对称...     

一种基于多项式的预失真算法

自适应预失真技术是用于补偿高功率放大器非线性失真的一种有效技术.文中介绍了用LMS算法来实现的自适应预失真,以补偿功率放大器的非线性.计算机仿真结果表明,该自适应预失真技术具有实现复杂度低,收敛速度快的特点.     

A dual-mode analog baseband with digital-assisted DC-offset calibration for WCDMA/GSM receivers

A dual-mode analog baseband with digital-assisted DC-offset calibration(DCOC) for WCDMA/GSM receiver is presented.A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC-offset component only.This method has no bandwidth sacrifice.After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm.The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz.Total baseband gain can be programmed from 6 to 54 dB.The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm~2.     

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.