一种高性能Folded-Cascode运算放大器的设计

介绍了一种高性能Foldcd-Cascode运放的电路结构,它具有先进的偏置电源结构以调节输出动态幅度、动态开关电容反馈电路用于控制运放输出端的稳定性、合理地关断电路以降低电路非工作时的功耗等特点.运用HSPICE对电路进行了模拟,并给出了结果.     

OrCAD PSpice在模拟电子技术教学应用中的实践

讨论了传统模拟电子技术教学和实验设计的现状,以双极性结型晶体共射极放大器为例子,对OrCAD PSpice仿真技术在模拟教学中的应用进行了探讨。基于OrCAD PSpice仿真技术在很多方面能弥补传统教学的不足,指出先进的模拟电路仿真技术对于模拟电子教学具有重要意义。     

利用DAC设计数控信号发生器

利用数模转换器可构成频率精度高并且可程控的信号发生器。本电路主要由计数器CD4029产生稳定的八路数字信号输出，经数模转换器AD7528输出模拟信号，再经运放变换，从电路的不同的输出端分别实现了三角波、矩形波、正弦波输出，从而实现了信号发生器的数字控制。     

一个1.2伏CMOS0.13微米工艺19.2毫瓦10位30兆采样率流水线模数转换器

A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented. For the sake of lower power and area, the pipelined stages are scaled in current and area, and op amps are shared between the successive stages. The ADC is realized in the 0.13-μ m 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range, poor analog characteristic devices, the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference. Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio, 67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal. The FoM is 0.33 pJ/step. The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB, respectively. The ADC core area is 0.94 mm².     

一种功率放大器预失真技术

预失真技术在现代功率放大器研究和设计中已成为一个重要的课题。本文基于功率放大器模拟预失真技术以及数字预失真技术的特征,提出了一种全新的预失真技术及实现方法。理论分析和计算机仿真结果表明：本文所提出的功率放大器预失真技术在方案上是可行的,并且对消性能较好。从实验结果可以看出,采用了这种预失真技术的功率放大器,成本、线性等关键指标与模拟预失真和数字预失真功率放大器相比有一个很好的折衷,综合性价比较高。     

基于产业人才培养的模拟电路课程优化研究——放大电路教学研究

模拟电路是电类专业的主干课程,课程内容多、学习难度大。基于产业人才培养的模拟电路课程教学与传统的模拟电路教学有很大的不同,基于产业人才培养的模拟电路课程教学应该侧重产业需求和实用性。在模拟电路的教学中应尽可能满足企业对模拟电路实用性的要求,优化课程内容,培养学生模拟电路应用能力,掌握各种器件构成的放大电路的分析、设计及其应用。     

FPGA Implementation of a Power Amplifier Linearizer for an ETSI-SDR OFDM Transmitter

Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array （FPGA） platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.     

PLC控制系统干扰现象及其防范措施

对可编程逻辑控制器(PLC)控制系统在实际应用中出现的温度信号显示不正常、模拟量信号漂移、开关量输入信号无反应、接地故障等干扰现象进行了分析,提出了解决方法及其防范措施,为电厂处理同类问题提供参考。     

CMOS四路可加权高频模拟开关的设计和研究

介绍了一种可对高频信号进行取样、加权、控制、叠加的模拟信号处理开关集成电路,通过两个高宽长比的高跨导NM O S晶体管可实现权值的粗调和微调。该电路采用标准0.6μm CM O S工艺制造。测试结果表明:该电路的工作频段为50~250 MH z时,导通时最小插入损耗约为-5.0~-10.5 dB,关断时隔离度可达-40.5~-23.4 dB左右;其连续可调的加权动态范围最大值为21.3 dB。     

毫米波线性化固态功放的研制

研制了工作于Ka频段的10 W线性化固态功放.采用预失真技术的线性化单元主要由一个肖特基二极管和一个电容并联构成,具有增益扩展和相位延迟的特性,并且其增益和相位特性具有可调性.将其应用于工作频率为30 GHz、输出功率为10 W的功放,双音激励信号频率间隔为5 MHz,三阶互调(IMD3)可以改善15 dBc.