Synthesizing Energy-Efficient Embedded Systems with LOPOCOS

In this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that include dynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimization steps during design space exploration for DVS enable architectures. The optimization steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimization for scheduling and communication mapping based on genetic algorithm, optimizes simultaneously execution order and communication mapping towards the utilization of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimizationsteps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm.     

Determination of generation lifetime fromC-t transients under linear voltage ramp bias

When a linear voltage ramp is applied to the gate of a MOS capacitor, a capacitancetime (C-t) transient is observed. The MOS capacitor is biased into strong inversion before applying the voltage ramp in order to eliminate surface generation. FromC-t transient curve obtained experimentally the minority carrier generation lifetime in semiconductor can be determined. The experimental results show that for the same sample the lifetimes extracted fromC-t curves under varying voltage sweep rates are close each other, and they are consistent with the lifetimes extracted by saturation capacitance method.     

定电流对LED的重要性

高功率超高亮度LED已经开始大量应用.要实际体现LED(尤其是高功率超高亮度LED)的优点,采用定电流驱动方式必要条件之一.     

基于小波熵的电容器扰动识别和定位

对投电容器扰动识别和定位的方法进行了改进。针对其他此类方法的不足，比如在电压幅值低时投电容器扰动的识别、定位“可信度不高”等，文中通过提取小波变换的特定层的系数，对需要识别的电容器扰动的分解信号相对增强，而其他扰动的分解信号相对减弱，然后再提取熵特征值，结果表明它可以作为识别低电压时投电容器扰动的依据。在对电容器扰动进行定位时，参考了功率和能量定位法，并对其进行了改进。仿真分析证明，在电压幅值较低时，可以准确和可靠地对电容器扰动进行识别和定位。     

电子辐照加速器大功率工频高压电源

文章介绍目前两种用于烟气脱硫加速器的不同形式直流高压电源，分析了它们各自的特点。针对它们存在的不足之处，提出了一种全新的倍压型桥式整流线路，并对此线路进行了理论推导和计算机模拟仿真。     

Lowering the erosion wear of long blades of the last stages by optimum hanging

Problems of optimum hanging of long rotor blades of the last stages of steam turbines are considered. Causes of nonuniform erosion wear of the inlet edges connected with inaccurate location of holes for the external damper coupling on the chord of the profile are determined. Methods for optimizing the hanging of blades for raising the reliability of the last stages are suggested. Main results of hanging performed with the help of a specially developed “LIBRA” soft hardware are presented. __________ Translated from élektricheskie Stantsii, No. 11, November 2006, pp. 36–41.     

关于缩短大电流开关二极管反向恢复时间的研究

通过长期的工作实践，阐述了适当条件下的金扩散对缩短反向恢复时间，提高二极管2CK28开关速度，满足了反向恢复时间，改善了二极管的反向特性。     

一种升压式PFM DC-DC转换器的设计

讨论了一种PFM升压式DC－DC电压转称器的设计，重点对其关键的基准电压产生，振荡控制信号产生及比较器设计进行了分析，并采用3μmCOMOS工艺完成芯片的设计。     

脉冲激光沉积SrBi2Ta2O9铁电薄膜电容特性研究

用ＰＬＤ方法成功地制备了ＳＢＴ铁电薄膜，并制作成Ｐｔ／ＳＢＴ／Ｐｔ薄膜电容器。ＳＢＴ薄膜的晶面取向以（００８）和（１１５）为主。在５Ｖ电压下，极化反转，并且得到较饱和的电滞回线，剩余极化强度和矫顽电场分别为８４μＣ／ｃｍ２和５７ｋｖ／ｃｍ。ＩＶ特性测试显示两个对称的双稳峰，并得到零电压下，面积为３１４×１０４μｍ２，厚度为０３５μｍ的电容器，电容约为５６０ｐＦ，介电常数约为６００。疲劳测试表明Ｐｔ／ＳＢＴ／Ｐｔ具有优良的抗疲劳特性。     

A novel method of suppressing the inrush current of transformers by using a series‐connected voltage‐source PWM converter

This paper proposes a novel method of suppressing the inrush current of transformers. A small‐rated voltage‐source PWM converter is connected in series to the transformers through a matching transformer. As the connected PWM converter serves as a resistor for the source current, no inrush phenomena occurs. The required rating of the PWM converter, which serves as the damping resistor for the inrush phenomena, is 1/400 that of the main transformers in single‐phase circuits. In three‐phase circuits, it is 1/900. The basic principle of the proposed method is discussed. Digital computer simulation is implemented to confirm the validity and excellent practicability of the proposed method using the PSCAD/EMTDC. A prototype experimental model is constructed and tested. The experimental results demonstrate that the proposed method can perfectly suppress the inrush phenomena. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 157(4): 56–65, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20174