全文获取类型
收费全文 | 30912篇 |
免费 | 4555篇 |
国内免费 | 2534篇 |
专业分类
电工技术 | 8840篇 |
技术理论 | 2篇 |
综合类 | 2434篇 |
化学工业 | 1314篇 |
金属工艺 | 353篇 |
机械仪表 | 1357篇 |
建筑科学 | 789篇 |
矿业工程 | 398篇 |
能源动力 | 3268篇 |
轻工业 | 282篇 |
水利工程 | 773篇 |
石油天然气 | 938篇 |
武器工业 | 207篇 |
无线电 | 4051篇 |
一般工业技术 | 1744篇 |
冶金工业 | 498篇 |
原子能技术 | 160篇 |
自动化技术 | 10593篇 |
出版年
2024年 | 241篇 |
2023年 | 682篇 |
2022年 | 1085篇 |
2021年 | 1330篇 |
2020年 | 1370篇 |
2019年 | 1194篇 |
2018年 | 1010篇 |
2017年 | 1350篇 |
2016年 | 1350篇 |
2015年 | 1487篇 |
2014年 | 2187篇 |
2013年 | 1982篇 |
2012年 | 2364篇 |
2011年 | 2455篇 |
2010年 | 1831篇 |
2009年 | 1935篇 |
2008年 | 1856篇 |
2007年 | 1984篇 |
2006年 | 1613篇 |
2005年 | 1546篇 |
2004年 | 1283篇 |
2003年 | 1029篇 |
2002年 | 909篇 |
2001年 | 765篇 |
2000年 | 613篇 |
1999年 | 485篇 |
1998年 | 371篇 |
1997年 | 300篇 |
1996年 | 266篇 |
1995年 | 248篇 |
1994年 | 191篇 |
1993年 | 142篇 |
1992年 | 114篇 |
1991年 | 91篇 |
1990年 | 63篇 |
1989年 | 42篇 |
1988年 | 31篇 |
1987年 | 24篇 |
1986年 | 23篇 |
1985年 | 32篇 |
1984年 | 26篇 |
1983年 | 17篇 |
1982年 | 14篇 |
1981年 | 11篇 |
1980年 | 18篇 |
1979年 | 11篇 |
1978年 | 10篇 |
1977年 | 8篇 |
1976年 | 3篇 |
1974年 | 3篇 |
排序方式: 共有10000条查询结果,搜索用时 8 毫秒
31.
分析了现有移动通信网络存在的问题,阐述了第2代移动通信核心网向第3代移动通信核心网演进的必然性:讨论了第2代移动通信核心网向第3代移动通信核心网演进所采用的演进策略,介绍了两种可供选择的全IP核心网络的参考结构。 相似文献
32.
33.
碾压混凝土坝施工进度与质量控制的新措施 总被引:1,自引:1,他引:0
碾压混凝土重力坝和拱坝由于连续施工的坝体混凝土体积大,施工期间需要采取较为严格的温度控制措施,而所采取的温控措施是否有效,目前尚没有一个能够用于实际施工过程的快速有效的评估方法和方式,不能根据已施工坝体内的实际情况来控制施工进度和质量。利用分布式光纤温度测量系统来快速地获得坝体混凝土内部的大量温度信息,进而实际标定温度仿真程序并通过标定过程模拟拟施工的连续碾压层,以检验其温控措施的有效性。通过坝体内部的温度、温度变化速率和梯度来达到实时控制坝体碾压上升速度、坝面和仓面养护、以及冷缝灌浆处理等目的。 相似文献
34.
本文介绍了汉英机器翻译系统中从中间媒介语言生成英语的生成系统的词汇结构和功能,描述了生成系统各个层次之间的转换原理。为了说明清楚,在叙述中注意了列举从中间媒介中间媒介语言到目标语句的生成实例。 相似文献
35.
本文给出从指称语义自动生成解释器后端的一种技术.解释器被表示成PASCAL_like形式. 相似文献
36.
This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES. 相似文献
37.
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach. 相似文献
38.
本文结合为某机械厂开发的实用计算机辅助工艺设计系统(JJCAPP),论述了一种兼有派生式和创成式特点的综合式工艺自动设计方法. 相似文献
39.
Marcus T. Schmitz Bashir M. Al-Hashimi Petru Eles 《Design Automation for Embedded Systems》2002,6(4):401-424
In this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that include dynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimization steps during design space exploration for DVS enable architectures. The optimization steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimization for scheduling and communication mapping based on genetic algorithm, optimizes simultaneously execution order and communication mapping towards the utilization of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimizationsteps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm. 相似文献
40.