Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

三相电压型SVPWM整流器的研究与设计

分析了三相整流器工作原理及数学模型的转换,研究了基于稳态条件下满足功率指标和瞬态电流跟踪指标的电感设计,提出了一种根据有功电流最大上升速率和直流电压最大下降速率对电容参数进行设计的方法,为后续研究整流器的高速实时仿真平台奠定理论基础。     

基于一种新型嵌入式系统级芯片的无线数据采集系统的设计

nRF24E1收发器是NordicVLSI推出的一种系统级芯片,是世界上第一个全球2·4GHz通用的、完整的低成本射频系统级芯片;在遥控、遥测、汽车电子及无线数据采集方面有广阔应用前景。介绍了新型嵌入式系统级芯片24E1的结构及其各部分的功能,并以24E1为核心部件构建了一种新型的8路无线数据采集系统。并在此基础上进一步说明了该无线数据采集系统的硬件组成及其软件的工作流程和详细的程序结构。同传统的无线数据采集系统相比,有独特的自身优势。     

钟控神经MOS管的改进及其在多值电路中的应用

首先对钟控神经MOS管进行研究,提出了相应的改进方法.然后采用此改进的钟控神经MOS管设计了一种新型多值触发器.与传统的触发器相比较,此多值触发器具有结构简单、速度快、功耗低等特点;而且无需改变电路结构就可实现不同基的多值触发器.PSPICE模拟证明了所设计的电路具有正确的逻辑功能.     

多层陶瓷外壳的失效分析和可靠性设计

文章对多层陶瓷外壳的失效模式,包括陶瓷底座断裂失效、绝缘电阻失效、断路和短路失效、外引线和无引线外壳引出端焊盘与外电路连接失效、电镀层锈蚀失效、密封失效、键合和芯片剪切失效和使用不当造成失效等进行讨论,并对这些失效的失效机理进行了分析,根据以上的失效模式及其失效机理分析,对多层陶瓷外壳的可靠性设计进行了探讨。     

一种新型全向高增益印刷天线的设计

设计了一种新型全向高增益印刷天线。该天线采用平衡微带线作馈线．以印刷振子作为辐射单元,末端采用匹配电路对其输入阻抗进行匹配。用商用软件AnsoftHFSS对天线的特性进行了仿真计算。比较表明,测试结果优于仿真结果。该天线工作在SCDMA频段（1785～1805MHz）,其H面不圆度小于1dB,中心频率下增益大于12dB,满足了设计要求。     

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated.

基于单片机和CPLD的控制系统设计

给出了控制系统的设计框图,对每一个模块的功能进行了分析,利用单片机、CPLD和数字化技术完成了系统设计,最后给出了分析结果.     

Cross-layer modeling of adaptive wireless links for QoS support in heterogeneous wired-wireless networks

Future wired-wireless multimedia networks require diverse quality-of-service (QoS) support. To this end, it is essential to rely on QoS metrics pertinent to wireless links. In this paper, we develop a cross-layer model for adaptive wireless links, which enables derivation of the desired QoS metrics analytically from the typical wireless parameters across the hardware-radio layer, the physical layer and the data link layer. We illustrate the advantages of our model: generality, simplicity, scalability and backward compatibility. Finally, we outline its applications to power control, TCP, UDP and bandwidth scheduling in wireless networks. The work by Q. Liu and G. B. Giannakis are prepared through collaborative participation in the Communications and Networks Consortium sponsored by the U.S. Army Research Laboratory under the Collaborative Technology Alliance Program, Cooperative Agreement DAAD19-01-2-0011. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon. The work by S. Zhou is supported by UConn Research Foundation internal grant 445157. Qingwen Liu (S’04) received the B.S. degree in electrical engineering and information science in 2001, from the University of Science and Technology of China (USTC). He received the M.S. degree in electrical engineering in 2003, from the University of Minnesota (UMN). He currently pursues his Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Minnesota (UMN). His research interests lie in the areas of communications, signal processing, and networking, with emphasis on cross-layer analysis and design, quality of service support for multimedia applications over wired-wireless networks, and resource allocation. Shengli Zhou (M’03) received the B.S. degree in 1995 and the M.Sc. degree in 1998, from the University of Science and Technology of China (USTC), both in electrical engineering and information science. He received his Ph.D. degree in electrical engineering from the University of Minnesota, 2002, and joined the Department of Electrical and Computer Engineering at the University of Connecticut, 2003. His research interests lie in the areas of communications and signal processing, including channel estimation and equalization, multi-user and multi-carrier communications, space time coding, adaptive modulation, and cross-layer designs. He serves as an associate editor for IEEE Transactions on Wireless Communications since Feb. 2005. G. B. Giannakis (Fellow’97) received his Diploma in Electrical Engineering from the National Technical University of Athens, Greece, 1981. From September 1982 to July 1986 he was with the University of Southern California (USC), where he received his MSc. in Electrical Engineering, 1983, MSc. in Mathematics, 1986, and Ph.D. in Electrical Engineering, 1986. After lecturing for one year at USC, he joined the University of Virginia in 1987, where he became a professor of Electrical Engineering in 1997. Since 1999 he has been a professor with the Department of Electrical and Computer Engineering at the University of Minnesota, where he now holds an ADC Chair in Wireless Telecommunications. His general interests span the areas of communications and signal processing, estimation and detection theory, time-series analysis, and system identification -- subjects on which he has published more than 200 journal papers, 350 conference papers and two edited books. Current research focuses on transmitter and receiver diversity techniques for single- and multi-user fading communication channels, complex-field and space-time coding, multicarrier, ultra-wide band wireless communication systems, cross-layer designs and sensor networks. G. B. Giannakis is the (co-) recipient of six paper awards from the IEEE Signal Processing (SP) and Communications Societies (1992, 1998, 2000, 2001, 2003, 2004). He also received the SP Society’s Technical Achievement Award in 2000. He served as Editor in Chief for the IEEE SP Letters, as Associate Editor for the IEEE Trans. on Signal Proc. and the IEEE SP Letters, as secretary of the SP Conference Board, as member of the SP Publications Board, as member and vice-chair of the Statistical Signal and Array Processing Technical Committee, as chair of the SP for Communications Technical Committee and as a member of the IEEE Fellows Election Committee. He has also served as a member of the IEEE-SP Society’s Board of Governors, the Editorial Board for the Proceedings of the IEEE and the steering committee of the IEEE Trans. on Wireless Communications.     

Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design

Temperature affects not only the performance but also the power, reliability, and cost of the embedded system. This paper proposes a temperature-aware task allocation and scheduling algorithm for MPSoC embedded systems. Thermal-aware heuristics are developed, and a temperature-aware floorplanning tool is used to reduce the peak temperature and achieve a thermally even distribution while meeting real time constraints. The paper investigates both power-aware and thermal-aware approaches to the task allocation and scheduling. The experimental results show that the thermal-aware approach outperforms the power-aware schemes in terms of maximal and average temperature reductions. To the best of our knowledge, this is the first MPSoC task allocation and scheduling algorithm that takes temperature into consideration.

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