Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.     

Cooperation between memory systems: Acetylcholine release in the amygdala correlates positively with performance on a hippocampus-dependent task.

The present experiment examined the relationship between release of acetylcholine (ACh) in the amygdala and performance on a hippocampus-dependent spatial working memory task. Using in vivo microdialysis, the authors measured ACh release in rats during testing on a spontaneous alternation task. Amygdala ACh release was positively correlated with performance on the hippocampus-dependent task. These findings suggest that activation of the amygdala promotes processing in other neural systems important for learning and memory. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Random errors caused by temperature in magnitude of principal strains evaluated ith 3-element strain gauge rosettes

The effects of the uncertainties associated ith the apparent strain and gauge factor data, given by the manufacturer, in the evaluation of principal strains are examined. Principal strains are obtained by a reduction of the strains measured ith electrical resistance strain gauge rectangular or delta rosettes. The theoretical analysis points out the relevance of the effects caused.     

TMS320C67系列EMIF与异步FIFO存储器的接口设计

介绍了TI公司TMS320C67系列DSP的EMIF(外部存储器接口)与异步FIFO(先进先出)存储器的硬件接口设计,着重描述了用EDMA(扩展的直接存储器访问)方式读取FIFO存储器数据的软件设计流程,最后说明了在选择FIFO存储器时应注意的问题.由于EMIF的强大功能,不仅具有很高的数据吞吐率,而且可以与不同类型的同步、异步器件进行无缝连接,使硬件接口电路简单,调试方便.运用EDMA的方式进行数据传输,由EDMA控制器完成DSP存储空间内的数据搬移,这样可以最大限度地节省CPU的资源,提高整个系统的运算速度.     

SHS of shape memory CuZnAl alloys

Aiming at preparation of shape memory alloys (SMAs), we explored the SHS of Cu_{1 − x} Zn_{1 − y} Al_{1 − z} alloys (0.29 < x < 0.30, 0.74 < y < 0.75, and 0.83 < z < 0.96). The most pronounced shape memory effect was exhibited by the alloys of the following compositions (wt %): (1) Cu(70.6)Zn(25.4)Al(4.0), (2) Cu(70.1)Zn(25.9)Al(4.0), and (3) Cu(69.9)Zn(26.1)Al(4.0). The effect of process parameters on the synthesis of CuZnAl alloys was studied by XRD, optical microscopy, and scanning electron microscopy (SEM). The grain size of CuZnAl was found to depend on the relative amount of the primary CuZn and AlZn phases. Changes in the transformation temperature and heat of transformation are discussed in terms of ignition intensity and compaction. Mechanism of the process depends on the level of the temperature attained relative to the melting point of components. At the melting point of AlZn, the process is controlled by the solid-state diffusion of AlZn into a product layer. The ignition temperature for this system depends on the temperature of the austenite-martensite transformation in CuZnAl alloys. The composition and structure of the products was found to markedly depend on process parameters. The SHS technique has been successfully used to prepare a variety of SMAs.      

A Nonvolatile Organic Memory Device Using ITO Surfaces Modified by Ag‐Nanodots

We report on a single‐layer organic memory device made of poly(N‐vinylcarbazole) embedded between an Al electrode and ITO modified with Ag nanodots (Ag‐NDs). Devices exhibit high ON/OFF switching ratios of 10⁴. This level of performance could be achieved by modifying the ITO electrodes with some Ag‐NDs that act as trapping sites, reducing the current in the OFF state. Temperature dependence of the electrical characteristics suggest that the current of the low‐resistance state can be attributed to Schottky charge tunnelling through low‐resistance pathways of Al particles in the polymer layer and that the high‐resistance state can be controlled by charge trapping by the Al particles and Ag‐NDs.     

Maltreated children's memory: Accuracy, suggestibility, and psychopathology.

Memory, suggestibility, stress arousal, and trauma-related psychopathology were examined in 328 3- to 16-year-olds involved in forensic investigations of abuse and neglect. Children's memory and suggestibility were assessed for a medical examination and venipuncture. Being older and scoring higher in cognitive functioning were related to fewer inaccuracies. In addition, cortisol level and trauma symptoms in children who reported more dissociative tendencies were associated with increased memory error, whereas cortisol level and trauma symptoms were not associated with increased error for children who reported fewer dissociative tendencies. Sexual and/or physical abuse predicted greater accuracy. The study contributes important new information to scientific understanding of maltreatment, psychopathology, and eyewitness memory in children. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

射频识别模块SMC51489在门禁系统中的应用

射频识别系统一般由三部分组成:电子标签(射频卡)、读取器和天线.正确快速的识别电子标签的标签号码,是门禁系统发挥其功能的先决条件.以无源低频射频卡识别模块SMC51489为例,介绍了对射频卡信息读取的原理和方法,并给出了相应的软件编程.实验证明该模块不仅具有较大的读卡距离,而且工作可靠.