Context Switching in a Run-Time Reconfigurable System

A distinguishing feature of reconfigurable computing over rapid prototyping is its ability to configure the computational fabric on-line while an application is running. Conventional reconfigurable computing platforms utilize commodity FPGAs, which typically have relatively long configuration times. Shrinking the configuration time down to the nanosecond region opens possibilities for rapid context switching and virtualizing the computational resources. An experimental context-switching FPGA, called the CSRC, has been created by BAE Systems, and gives researchers the opportunity to explore context-switching applications. This paper presents results obtained from constructing both control-driven and data-driven context switching applications on the CSRC device, along with unique properties of the run-time and compile-time environment.     

提高虚拟空间会议系统服务质量QoS的若干技术

虚拟空间会议系统是视频会汉系统发展的最高形式．本文结合作者研究工作，通过分析与视频会议系统服务质量相关的技术，提出了基于VST系统的相关技术策略，这些策略能够有效地提高VST系统的服务质量．     

新型CAMAC智能模数变换插件设计

介绍了新型CAMAC智能模数变换插件的设计。该插件研制的目的的是和来替代正在BESⅡ上使用的智能型模糊控制插件。设计中使用了DSP和FPGA等技术。     

JAVA新类库中Swing的事件传送机制

ＳＵＮ公司最新发布的一套ＡＰＩ中的Ｓｗｉｎｇ组件集采用了ＭＶＣ结构，其中Ｍ、Ｖ、Ｃ三者间的事件传送及与外界的通信机制相当重要。本文从Ｓｗｉｎｇ的组件如何响应外部事件、如何处理自身的变化及如何把自身变化传递给外界三个方面详细阐述Ｓｗｉｎｇ的事件传送机制。     

用FPGA实现线阵红外探测器的奇偶校正

法国Sofradir公司生产的288×4红外焦平面阵列(IRFPA)具有很高的探测灵敏度,是军用红外系统的理想器件。由于器件本身的结构特点,在使用时需要进行奇偶校正。该电路的控制逻辑比较复杂,实现的方法有三种:用传统的中小规模集成电路实现,这种实现方法难度比较大;用CPLD或FPGA做逻辑,其它部分用中小规模集成电路,这种实现方法布线比较困难;所有电路全部用FPGA实现,这种实现方法布线简单,电路集成度高,体积小,功耗低,可靠性好,是最佳实现方案。文中就是用这种方案实现了该探测器的奇偶校正电路。     

A Scalable Interconnection Network Architecture for Petaflops Computing

Extrapolating technology advances in the near future, a computer architecture capable of petaflops performance will likely be based on a collection of processing nodes interconnected by a high-performance network. One possible organization would consist of thousands of inexpensive, low-power symmetric multiprocessor (SMP) nodes. Each node will inject data into the interconnection network at a very large rate and consequently, the interconnect scheme is one of the most crucial design issues affecting system performance. This paper describes the 2D simultaneous optical multiprocessor exchange bus (2D SOME-Bus) which has the potential to become the basis of a high-end computer architecture capable of petaflops performance. It consists of N horizontal, N vertical 1D SOME-Bus networks, and N ² nodes. Each node is connected to one horizontal and one vertical 1D SOME-Bus. Each of N nodes connected to one 1D SOME-Bus has a dedicated broadcast channel and an input channel interface based on an array of N receivers monitoring all N channels and allowing multiple simultaneous broadcasts. In the 2D SOME-Bus, messages being broadcast on one Bus can be broadcast in a cut-through manner on one or more Buses in the other dimension. This paper describes the optoelectronic devices and technology which make the 2D SOME-Bus possible, and the network interface organization. It also presents simulation results which compare the performance of the 2D SOME-Bus, the 1D SOME-Bus, the crossbar and the torus under the message-passing paradigm.     

基于两相正交开关霍尔传感器的混合型转子位置预估方案的FPGA实现

提出了一种利用两相正交的锁定型开关霍尔传感元件对正弦波永磁同步电动机转子位置进行预估计的新型数字电路设计方案,并进行了误差分析,最后在可编程逻辑器件FPGA上完成了布局布线和时序验证.仿真和实验结果表明稳态时能够获得比较高的位置精度,而且性价比比较合理,可以与其他功能模块或IP芯核相结合应用在低成本的简易正弦驱动场合.     

EDA设计技术与方法(Ⅰ)──EDA方法及其进展

ＥＤＡ是现代电子学的标志。本研究对 ＥＤＡ设计方法及其发展进行了综述。     

图像传感器数据采集与显示系统设计研究

随着智能小区门禁系统视频监控与远程控制功能的发展,高清图像传感器应用日益普及,为安全监控提供高质量图像。研究以现场可编程门阵列(FPGA)为核心的图像采集、显示与控制系统,作为门禁系统的核心电路,对FPGA配置OV3640控制寄存器方法进行了设计,并使用行场与像素脉冲来控制同步采集传感器输出的视频数据,图像实时显示在液晶显示屏上。调试结果表明:传感器配置方法及实时采集算法可行,能够满足高清图像拍摄与显示功能。更多还原     

基于FPGA的分布式算法FIR滤波器设计

FIR滤波器具有许多优点,是数字信号处理系统中基本的元件。本文比较了目前FIR滤波器硬件实现的几种方法,详细研究了基于FPGA、采用分布式算法实现FIR滤波器的原理和方法,设计了一个32阶线性相位FIR滤波器,并用VHDL语言对其进行了描述。此滤波器采用串行加法器将数据进行预相加,从而将滤波器的规模减半。其主要部分——乘累加单元,采用LUT查找表结构,将乘法运算转换为查表操作,提升处理速度。最后进行了硬件仿真,结果证明,这一方法是可行且高效的。