基于1553B和外部FLASH实现星上FPGA配置

太阳辐射监测仪作为某卫星载荷之一,其控制系统主要由DSP+FPGA组成,文章利用1553B和外部Flash实现了系统上电后自动配置FPGA;首先,利用1553B通讯芯片上传FPGA和DSP代码到外部RAM,并通过DSP烧写程序分别烧写到Flash的合理区域;系统上电后,DSP从Flash 0x0地址运行,初始化后运行FPGA配置程序,实现FPGA的动态配置;避免了FPGA跑飞后需要重新上电和归零,提高了系统的可靠性;省去了FPGA专用配置EPROM芯片,简化结构,降低了系统成本;实践证明,FPGA加载时间约2分钟,可定时加载或命令控制加载,该方法简单实用,适合星上载荷使用。     

基于UART的智能卡接口IP核设计

分析了UART核的结构和智能卡的传输协议,提出一种基于UART核的智能卡接口IP核的设计。该设计以成熟的UART核为基础,无需编写异步串口的时序与接口逻辑,仪在串口核中增加收发缓冲器和协议处理等模块,减少了工作量并缩短了开发周期。最后对所设计的IP核进行仿真和实际测试,结果表明该IP核设计正确,运行稳定,适合在多卡系统中应用。     

探海侯之死

在北京团城的城台上,有几株古松,相传是辽金遗物。清代乾隆皇帝给三棵古树封赐了爵位。十多年前,团城搞修缮,建筑队的某位工人把生石灰堆在名为“探海侯”的松树周围,生石灰化光了,古树死了。     

基于被动测量的高速网络管理系统

文章介绍了,面向大规模宽带IP网络的运维和管理需求,以大规模网络流量测量和知识挖掘为基础,研究基于分布式流量测量的新一代宽带网络管理架构,采用网络被动模式测量和主动采集技术手段,实现对高速网络的性能、状态和行为的管理,并对网络测量技术的发展及现状、系统的架构、关键技术和应用情况作了详细阐述,明确下一步研究工作的目标。     

提高定点精度的FPGA信号处理算法

为了满足速度、功耗等诸多限制的要求,数字信号处理算法常使用FPGA实现。而实现时由于硬件特点,通常将浮点运算转换成定点运算,但定点转换设计流程复杂、周期长,且存在数据范围和精度之间的矛盾。利用浮点数的优点,本文改进了基于FPGA的定点数的基本运算规则,有效解决了上述矛盾。本文详细论述了实现移位、加/减、乘、除基本运算模块的方法和步骤,最后以FIR数字滤波器为设计实例。仿真结果表明:改进的定点数算法比定点运算误差小、精度高、数据范围宽,能有效地防止溢出。     

Past and future of software architectural decisions – A systematic mapping study

ContextThe software architecture of a system is the result of a set of architectural decisions. The topic of architectural decisions in software engineering has received significant attention in recent years. However, no systematic overview exists on the state of research on architectural decisions.ObjectiveThe goal of this study is to provide a systematic overview of the state of research on architectural decisions. Such an overview helps researchers reflect on previous research and plan future research. Furthermore, such an overview helps practitioners understand the state of research, and how research results can help practitioners in their architectural decision-making.MethodWe conducted a systematic mapping study, covering studies published between January 2002 and January 2012. We defined six research questions. We queried six reference databases and obtained an initial result set of 28,895 papers. We followed a search and filtering process that resulted in 144 relevant papers.ResultsAfter classifying the 144 relevant papers for each research question, we found that current research focuses on documenting architectural decisions. We found that only several studies describe architectural decisions from the industry. We identified potential future research topics: domain-specific architectural decisions (such as mobile), achieving specific quality attributes (such as reliability or scalability), uncertainty in decision-making, and group architectural decisions. Regarding empirical evaluations of the papers, around half of the papers use systematic empirical evaluation approaches (such as surveys, or case studies). Still, few papers on architectural decisions use experiments.ConclusionOur study confirms the increasing interest in the topic of architectural decisions. This study helps the community reflect on the past ten years of research on architectural decisions. Researchers are offered a number of promising future research directions, while practitioners learn what existing papers offer.     

一种基于多核嵌入式系统的TD-LTE同步校正方法

针对TD-LTE系统中同步性错误随机发生的问题,提出了一种通过ARM+DSP+FPGA平台的嵌入式系统实现帧号和原语的同步校正方法。该方法基于TD-LTE射频一致性测试仪表硬件平台,通过该嵌入式系统中ARM、DSP、FPGA间的协调工作,由GPMC模块通过帧号和原语两方面对系统同步性进行校正。在TD-LTE射频一致性测试仪表硬件平台中进行了验证,结果表明,该方法在实现帧号与子帧号同步校正的基础上明显提高了TD-LTE系统通信的稳定性。     

基于FPGA的高速数据存储系统优化设计

针对遥测系统数据记录装置中数据传输速率与存储速率不匹配的问题,提出Flash的并行存储方案,采用交替双平面的编程方式可以使得存储器的存储速率达到单片Flash最高存储速率的2倍,即60 MB/s;对控制单元FPGA内部双端口RAM的逻辑设计进行改进,解决了数据存储异常的现象。在数据回收方面,提出了多备份的设计思想和备用读数接口的设计方案,已在工程应用中得到成功实践,验证了该数据记录装置的可靠性。     

基于FPGA的高频全数字低电平系统算法实现

本套加速器高频低电平系统(LLRF)是中国ADS注入器II高频系统的原型机,其工作频率为162.5 MHz,以实现超导加速腔的幅度与相位稳定控制和谐振频率调节。该系统主要由射频前端和数字信号处理FPGA两部分组成。射频前端主要实现高频信号的上下变频和电平匹配;数字信号处理FPGA是系统的核心,主要完成射频信号幅值与相位的数字稳定控制,超导腔谐振频率控制,以及1 000 M以太网通信。在实验室环境下,对该系统进行了幅度和相位稳定度测试,相位稳定度峰峰值为±0.3°,有效值为0.09°,幅值相对稳定度峰峰值为±5×10-3,有效值为3.2×10-3,达到了设计要求。     

PMSS: A programmable memory system and scheduler for complex memory patterns

HPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. However, applications are getting more complex, with multiple kernels and complex data arrangements, generating overhead while scheduling/managing system resources. Due to this reason all classes of multi threaded machines–minicomputer to supercomputer–require to have efficient hardware scheduler and memory manager that improves the effective bandwidth and latency of the DRAM main memory. This architecture could be a very competitive choice for supercomputing systems that meets the demand of parallelism for HPC benchmarks. In this article, we proposed a Programmable Memory System and Scheduler (PMSS), which provides high speed complex data access pattern to the multi threaded architecture. This proposed PMSS system is implemented and tested on a Xilinx ML505 evaluation FPGA board. The performance of the system is compared with a microprocessor based system that has been integrated with the Xilkernel operating system. Results show that the modified PMSS based multi-accelerator system consumes 50% less hardware resources, 32% less on-chip power and achieves approximately a 19x speedup compared to the MicroBlaze based system.