Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.     

基于FPGA的高性能可编程数据平面研究综述

可编程数据平面(PDP)一方面支持网络应用的卸载与加速, 给网络应用带来了革命性的发展机遇; 另一方面支持新协议、新服务的快速实现和部署, 促进了网络创新和演进, 是近年来网络领域的研究热点. FPGA因其通用的计算架构、丰富的片内资源和扩展接口提供了多种可编程数据平面的具体实现, 支持更广范围的应用场景. 同时, FPGA还为探索更通用的可编程数据平面抽象提供了可能. 因此, 基于FPGA的可编程数据平面受到了学术界与产业界的广泛关注. 首先分类别阐述基于FPGA的可编程数据平面(F-PDP)抽象. 接着, 介绍基于F-PDP快速构建网络应用的关键技术的研究进展. 之后, 介绍基于F-PDP的新型可编程网络设备. 此外, 从提升网络性能、构建网络测量框架以及部署网络安全应用这3个方面, 详细梳理近年来基于F-PDP的应用研究成果. 最后, 探讨F-PDP未来可能的研究趋势.     

基于DeblurGAN的运动模糊图像盲复原算法研究

DeblurGAN方法利用条件生成对抗网络解决了端到端的图像去模糊问题,但存在图像边缘细节恢复不足以及鲁棒性不高的问题,针对此问题,提出一种基于DeblurGAN的运动模糊图像盲复原方法。在生成网络中,采用多尺度卷积核神经网络提取特征,并使用级联空洞卷积扩大神经元的感受野;采用自适配归一化方法代替原来生成器中使用的实例归一化方法。其次,引入了梯度图像L1损失,结合对抗损失和感知损失,将其作为图像去模糊的正则约束,使得生成图像的边缘特征更加清晰。实验结果表明,提出方法复原的图像峰值信噪比数值较DeblurGAN算法高出5.4%,结构相似性指标高出1%;在主观上清晰化效果较好,且消除了网格效应。     

基于改进支持向量回归的IGBT老化预测

为了准确预测绝缘栅双极型晶体管（IGBT）的老化状态,提出了一种基于改进鲸鱼优化算法（IWOA）优化支持向量回归（SVR）的IGBT老化预测方法。该方法提取IGBT集电极-发射极电压信号的时频域特征,通过核主成分分析（KPCA）降维将时频域特征融合成一个综合指标来表征IGBT的老化状态;针对鲸鱼优化算法（WOA）不足,在WOA的基础上引入Sobol序列种群初始化、惯性权重和反向学习策略,增强WOA的局部搜索能力和收敛速度;利用IWOA优化SVR的惩罚因子和核参数,并构建一种基于综合指标的IGBT预测模型。利用NASA Ames实验室的IGBT老化数据集对IWOA-SVR方法进行验证,结果表明,所构建IWOA-SVR预测模型可以更准确实现对IGBT的老化预测。     

5G 功放DPD 的FPGA 宽带实现及自动优化

5G 宽带功放数字预失真器(DPD)的FPGA 实现过程中,常遇到数字处理带宽不够和资源有限问题,对 此,文中提出一种基于双路并行数据流的数字预失真带宽扩展方法和基于Zynq Ultrascale+ MPSoC 的自动化模型优化 验证方法,可快速实现对5G 宽带功放线性化方案的优化。使用该并行处理结构的数字预失真器,克服了数字电路最 大时钟频率造成的对FPGA 线性化带宽的限制,使得数字预失真电路在每个时钟周期内可以处理更多的数据,不仅有 效地增加了数字处理带宽,而且降低了DPD 的功耗。然而,这种带宽增加以消耗更多硬件资源为代价,对此,文中同时 提出了对预失真非线性模型的在线自动优化方法,以简化非线性模型、降低DPD 的硬件资源开销。最后,在Zynq Ultrascale+ FPGA 实验平台上实现了具有两路并行数据处理的I-MSA 自优化数字预失真电路,采用100 MHz 的5G 新无 线电(NR)信号在2. 6 GHz 功率放大器上进行线性化实验验证,获得了满意的预失真性能,验证了所提方法的有效性。     

Flexible Nonvolatile Transistor Memory with Solution‐Processed Transition Metal Dichalcogenides

Nonvolatile field‐effect transistor (FET) memories containing transition metal dichalcogenide (TMD) nanosheets have been recently developed with great interest by utilizing some of the intriguing photoelectronic properties of TMDs. The TMD nanosheets are, however, employed as semiconducting channels in most of the memories, and only a few works address their function as floating gates. Here, a floating‐gate organic‐FET memory with an all‐in‐one floating‐gate/tunneling layer of the solution‐processed TMD nanosheets is demonstrated. Molybdenum disulfide (MoS₂) is efficiently liquid‐exfoliated by amine‐terminated polystyrene with a controlled amount of MoS₂ nanosheets in an all‐in‐one floating‐gate/tunneling layer, allowing for systematic investigation of concentration‐dependent charge‐trapping and detrapping properties of MoS₂ nanosheets. At an optimized condition, the nonvolatile memory exhibits memory performances with an ON/OFF ratio greater than 10⁴, a program/erase endurance cycle over 400 times, and data retention longer than 7 × 10³ s. All‐in‐one floating‐gate/tunneling layers containing molybdenum diselenide and tungsten disulfide are also developed. Furthermore, a mechanically‐flexible TMD memory on a plastic substrate shows a performance comparable with that on a hard substrate, and the memory properties are rarely altered after outer‐bending events over 500 times at the bending radius of 4.0 mm.     

有约束的登机门分配问题混合遗传算法

为解决机场航班对登机门有约束的分配问题,提出一种遗传算法与模拟退火算法相结合的混合算法。设计一种编码方法,采用一个向量作为一种登机门分配方案,向量的元素位置表示飞机,元素表示分配给该航班的登机门,同时设计了与编码相应的不需再修正的杂交和变异算子。为了增加算法的局部搜索能力,且尽量不增加计算的复杂度,将模拟退火算法和遗传算法并行作用于相应的子群,并探讨该算法的收敛性。模拟实验结果表明,该算法在计算结果与稳定性方面均优于其他算法。     

Lithium doping and gate dielectric dependence study of solution‐processed zinc‐oxide thin‐film transistors

Abstract— The effects of lithium (Li) doping concentration and gate dielectrics on the performance of solution‐processed zinc‐oxide (ZnO) thin‐film transistors (TFTs) has been investigated. ZnO films with strong c‐axis orientation and lower background conductivity was obtained with 15 at.% of Li. Different crystallization behavior of ZnO was observed in the case of various dielectric surfaces. The 15‐at.% Li‐doped ZnO films (thickness ～20 nm) prepared on SiO² and SiN^x were found to be present in crystalline form, whereas the film prepared on aluminum titanium oxide (ATO) was found to be amorphous. A field‐effect mobility of 1.81 cm²/V‐sec and an Ion/Ioff ratio of 2 × 10⁶ were obtained for the 15‐at.% Li‐doped ZnO TFTs with a bilayer gate dielectric of SiO² and SiN^x. The comparison of dielectric studies showed that the performance of TFTs prepared on SiN^x and ATO are higher than that of the TFTs prepared on SiO².     

高速脉冲信号源的设计与实现

高速脉冲信号源是数据采集系统的重要组成部分,常用于系统的自检与测试中.根据实际要求,提出了高速运放调理和高速电子开关两种方案.分别对高速运放、信号幅值调理、驱动电路和高速电子开关的选择进行了研究,给出了具体的硬件电路设计.并结合相关理论,分析了信号在传输过程中出现的反射现象,提出了符合要求的解决方案.此高速脉冲信号源已成功应用于某采集设备的自检和测试中,效果良好.     

一种基于TDC的相对频差测量方法

提出了一种基于时间/数字转换器( TDC)的频率差测量方法.该方法使用延迟链和参考时钟结合的TDC直接数字量化频率差.测量系统与非线性标定模块均在现场可编程门阵列( FPGA)中实现.为了对频率差检测精度进行评估,使用振荡器作为仿真输入信号进行了实验.结果显示:所提出的测量方法对ΔF/F的测量噪声可以达到1 ×10-8/ 槡Hz.在实验结果的基础上,对测量噪声的来源进行了分析.