MOS门电路测试过程中功率损耗最小化

MOS逻辑门电路的功率损耗与其门电路的输出翻转成正比。在测试过程中,输出节点反转速率远高于正常使用时,很容易造成电路损坏。因此,在测试过程中减少逻辑门输出翻转速率具有重要意义。文章提出减少MOS门输出翻转速率的一些方法,有助于有效解决这一问题。该方法具有实现简单、编程方便等优点。     

光电成像系统与人眼视觉的匹配问题

以电视、激光成像和热成像系统为代表的光电成像系统在军事和民用上有着广泛的用途,但光电成像系统与人眼视觉的匹配问题仍是按现有理论和方法难以准确解释或定量描述的普遍问题。从理论上阐述了此问题的本质,说明了在这种匹配系统中存在系统的最佳匹配,且匹配状态直接影响光电成像系统的总体设计,并对如何描述这种关系进行一些说明和分析。     

Transmit antenna selection of correlated MIMO multiuser cognitive radio networks in Nakagami‐m fading channels

In this paper, we examine the impact of antenna correlation on transmit antenna selection with receive maximal ratio combining (TAS/MRC) in multiple‐input multiple‐output multiuser underlay cognitive radio network (MIMO‐MCN) over a Nakagami‐m fading environment. The secondary network under consideration consists of a single source and M destinations equipped with multiple correlated antennas at each node. The primary network composed of L primary users, each of which is equipped with multiple correlated antennas. For the considered underlay spectrum sharing paradigm, the transmission power of the proposed secondary system is limited by the peak interference limit on the primary network and the maximum transmission power at the secondary network. In particular, we derive exact closed‐form expressions for the outage probability and average symbol error rate of the proposed secondary system. To gain further insights, simple asymptotic closed‐form expressions for the outage probability and symbol error rate are provided to obtain the achievable diversity order and coding gain of the system. In addition, the impact of antenna correlation on the secondary user ergodic capacity has been investigated by deriving closed‐form expressions for the secondary user capacity. The derived analytical formulas herein are supported by numerical and simulation results to clarify the main contributions. Copyright © 2016 John Wiley & Sons, Ltd.     

Logic Design Validation via Simulation and Automatic Test Pattern Generation

We investigate an automated design validation scheme for gate-level combinational and sequential circuits that borrows methods from simulation and test generation for physical faults, and verifies a circuit with respect to a modeled set of design errors. The error models used in prior research are examined and reduced to five types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), wrong input errors (WIEs), and latch count errors (LCEs). Conditions are derived for a gate to be testable for GSEs, which lead to small, complete test sets for GSEs; near-minimal test sets are also derived for GCEs. We analyze undetectability in design errors and relate it to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. These experiments demonstrate that high coverage of the modeled errors can be achieved with small test sets obtained with standard test generation and simulation tools for physical faults.     

基于双平行MZM调制器和四波混频效应的高倍频微波信号的光学生成

提出了一种基于双平行Mach-Zehnder调制器(DPMZM ) 和半导体光放大器(SOA ) 的四波混频(FWM ) 效应的 24 倍频微波信号光学生成方案,具有覆盖频段高、系统结构简单 和 频谱纯度较高等优点。在本方案中,低频率的微波信号 通过 DPMZM 对光源进行调制,调节直流偏置点使 DPMZM 的两个子 MZM 和主 MZM 均偏置在最大传输点,抑制 所有 奇数边带,进一步调节两个子 MZM 的调制深度和移相器的相移,完全抑制光载波和二阶边带,得到±4阶光边带;再经 过 SOA 发生FWM效应 , 产生±12 光边带,经过光电探测器拍频后可获得 24 倍频的微波信号。最后,通过仿真实验, 以 10GHz 的微波信号为驱动信号,得到了 240GHz 的微波信号,验证了方案的可行性。     

本地网计费帐务系统的实现

计费帐务系统是本地电话网中最主要的管理系统之一 ,文中从新型计费帐务系统的建设目标出发 ,阐述了本地网内计费信息的在线数据采集 ,实时、准实时计费 ,集中式帐务系统的建设原则、实现方案、软件设计与体系结构。     

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

State-of-the-art devices in the consumer electronics market are relying more and more on Multi-Processor Systems-On-Chip (MPSoCs) as an efficient solution to meet their multiple design constrains, such as low cost, low power consumption, high performance and short time-to-market. In fact, as technology scales down, logic density and power density increase, generating hot spots that seriously affect the MPSoC performance and can physically damage the final system behavior. Moreover, forthcoming three-dimensional (3D) MPSoCs can achieve higher system integration density, but the aforementioned thermal problems are seriously aggravated. Thus, new thermal exploration tools are needed to study the temperature variation effects inside 3D MPSoCs. In this paper, we present a novel approach for fast transient thermal modeling and analysis of 3D MPSoCs with active (liquid) cooling solutions, while capturing the hardware-software interaction. In order to preserve both accuracy and speed, we propose a close-loop framework that combines the use of Field Programmable Gate Arrays (FPGAs) to emulate the hardware components of 2D/3D MPSoC platforms with a highly optimized thermal simulator, which uses an RC-based linear thermal model to analyze the liquid flow. The proposed framework offers speed-ups of more than three orders of magnitude when compared to cycle-accurate 3D MPSoC thermal simulators. Thus, this approach enables MPSoC designers to validate different hardware- and software-based 3D thermal management policies in real-time, and while running real-life applications, including liquid cooling injection control.     

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

前向多层神经网络模糊自适应算法

本文将模糊集理论与人工神经网络的研究相结合，提出一种模糊自适应ＢＰ算法，用典型异或问题与规模更大的打印机磁泄漏信息识别问题进行计算机模拟表明，该算法可使ＢＰ算法的收敛速度明显提高。此项工作为神经网络与模糊系统相结合探索了一条新的途径。     

二十一世纪通信发展走向

本文展望了２１世纪初社会、家庭、企业对通信的需求与通信在信息化社会中的重要地位，指出通信事业经营者应向社会提供什么样的通信业务（服务），应建设什么样的通信网来实现这些业务以及未来的网络需要哪些关键性通信技术来支持。