Oracle9i数据库安全管理机制剖析

数据库安全和数据安全机制是数据库开发设计者目前必须考虑的问题之一。Oracle9i数据库管理系统在数据库安全方面为数据库管理员和应用开发者提供了很好的安全机制。文章从不同侧面和角度讨论Oracle9i数据库系统的安全管理机制，为实施更安全更灵活的数据库安全策略提出了全方位的技术思路。     

碳/碳复合材料CVI工艺中热解碳形成机理的研究

对碳碳复合材料CVI或（CVD）工艺中热碳组织的类型，沉积机理等研究情况进行了简要的综述，并对其进一步研究提出了相应观点。     

絮凝剂品种对水下不分散混凝土性能影响的比较

通过电荷中和、吸附架桥和表面吸附分析了絮凝剂作用机理 ,运用絮凝机理进一步分析了絮凝剂在水泥体系中的作用以及絮凝剂对流动度的影响 ,从而对掺加JHP (纤维素类 )和Pj (丙烯类 )絮凝剂的水下不分散混凝土性能作了综合比较。掺Pj絮凝剂的混凝土 ,其坍扩度损失大 ,抗分散性能不如掺JHP絮凝剂的好 ;掺JHP絮凝剂的混凝土坍扩度在 3h内损失很小     

电厂设备维修现代化管理系统的建立

在总结传统电厂管理经验的基础上,借鉴国外先进管理经验形成的一套较适合国内电厂设备现代化维修管理系统,在生产实践中发挥了很好的作用。此管理系统将设备的各类任务(日常消缺、定检、大小修)与支持项目(材料、资料)等信息有机地结合起来,使设备信息做到全面、及时、准确,极大地缩短了任务传递时间,提高了任务执行效率,为管理者科学决策提供了有力的依据。     

橡胶卷材挤出连续硫化生产线的结构特色与工作原理

介绍了橡胶防水防腐卷材挤出连续硫化生产线的结构、特点和工作原理;指出在目前国内同类设备中,该生产设备具有先进性,并可替代引进设备。     

基于虚拟分割机制的多服务交换路由器的研究

本文提出了一处基于虚拟分割机制的可编程多服务器由器实现结构：PVSMR，并对它的三个层面的主要构成及其关键技术进行了深入研究。PVSMR基于一种有效而灵活的资源虚拟分割算法，它能够提供与多类应用相适应的、灵活的报文处理和转发控制能力。     

On the Automatic Recovery of Style-Specific Architectural Relations in Software Systems

The cost of maintaining a software system over a long period of time far exceeds its initial development cost. Much of the maintenance cost is attributed to the time required by new developers to understand legacy systems. High-level structural information helps maintainers navigate through the numerous low-level components and relations present in the source code. Modularization tools can be used to produce subsystem decompositions from the source code but do not typically produce high-level architectural relations between the newly found subsystems. Controlling subsystem interactions is one important way in which the overall complexity of software maintenance can be reduced.We have developed a tool, called ARIS (Architecture Relation Inference System), that enables software engineers to define rules and relations for regulating subsystem interactions. These rules and relations are called Interconnection Styles and are definedusing a visual notation. The style definition is used by our tool to infer subsystem-level relations in designs being reverse engineered from source code.In this paper we describe our tool and its underlying techniques and algorithms. Using a case study, we describe how ARIS is used to reverse engineer high-level structural information from a real application.     

淤泥质土状亚粘土的一些特征

珠江三角洲软土地区存在一种灰色亚粘土，其工程性能与淤泥、淤泥质土相似，但两者的物理力学性质却有明显的不同，这是一种在规范土名定义上处于过渡或边缘状态的粘性土，不是严格定义上的淤泥质土，也不是正常沉积的一般粘性土，土的强度和工程性质与淤泥质土类似，应该近沿海地区淤泥和淤泥质土对待，不应看成一般粘性土。     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.