全文获取类型
收费全文 | 40202篇 |
免费 | 5632篇 |
国内免费 | 3609篇 |
专业分类
电工技术 | 9491篇 |
技术理论 | 2篇 |
综合类 | 3810篇 |
化学工业 | 1905篇 |
金属工艺 | 545篇 |
机械仪表 | 2823篇 |
建筑科学 | 1239篇 |
矿业工程 | 582篇 |
能源动力 | 3576篇 |
轻工业 | 504篇 |
水利工程 | 1452篇 |
石油天然气 | 1003篇 |
武器工业 | 376篇 |
无线电 | 3980篇 |
一般工业技术 | 3259篇 |
冶金工业 | 655篇 |
原子能技术 | 141篇 |
自动化技术 | 14100篇 |
出版年
2024年 | 240篇 |
2023年 | 738篇 |
2022年 | 1273篇 |
2021年 | 1509篇 |
2020年 | 1699篇 |
2019年 | 1460篇 |
2018年 | 1308篇 |
2017年 | 1751篇 |
2016年 | 1801篇 |
2015年 | 1938篇 |
2014年 | 2816篇 |
2013年 | 3168篇 |
2012年 | 3148篇 |
2011年 | 3272篇 |
2010年 | 2333篇 |
2009年 | 2588篇 |
2008年 | 2478篇 |
2007年 | 2657篇 |
2006年 | 2211篇 |
2005年 | 1866篇 |
2004年 | 1545篇 |
2003年 | 1229篇 |
2002年 | 1013篇 |
2001年 | 881篇 |
2000年 | 780篇 |
1999年 | 615篇 |
1998年 | 458篇 |
1997年 | 435篇 |
1996年 | 368篇 |
1995年 | 317篇 |
1994年 | 270篇 |
1993年 | 200篇 |
1992年 | 200篇 |
1991年 | 171篇 |
1990年 | 137篇 |
1989年 | 108篇 |
1988年 | 75篇 |
1987年 | 39篇 |
1986年 | 33篇 |
1985年 | 39篇 |
1984年 | 53篇 |
1983年 | 30篇 |
1982年 | 30篇 |
1981年 | 27篇 |
1980年 | 32篇 |
1979年 | 31篇 |
1978年 | 19篇 |
1977年 | 21篇 |
1976年 | 7篇 |
1975年 | 6篇 |
排序方式: 共有10000条查询结果,搜索用时 15 毫秒
51.
52.
53.
As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis. 相似文献
54.
Erik Jan Marinissen 《Journal of Electronic Testing》2002,18(4-5):435-454
Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to system-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described. 相似文献
55.
56.
57.
证券组合的快车道问题研究 总被引:1,自引:1,他引:0
本文建立了新的证券组合最优控制模型,分析了证券市场长期投资过程中证券组合的快车道问题;提出了隐式规划的模拟退火方法,进行了快车道的仿真,这对于证券市场长期稳定运行和投资具有实际意义。 相似文献
58.
工业过程随机稳态优化控制算法的鲁棒性分析 总被引:1,自引:0,他引:1
本文给出了一种随机稳态优化算法的灵敏度分析,讨论算法解对参数变化的关系。这些参数代表系统结构参数或噪声向量的某些数字特征. 相似文献
59.
Pai H. Chou Jinfeng Liu Dexin Li Nader Bagherzadeh 《Design Automation for Embedded Systems》2002,7(3):205-232
Power-aware systems are those that must exploit a widerange of power/performance trade-offs in order to adapt to the power availabilityand application requirements. They require the integration of many novel powermanagement techniques, ranging from voltage scaling to subsystem shutdown.However, those techniques do not always compose synergistically with eachother; in fact, they can combine subtractively and often yield counterintuitive,and sometimes incorrect, results in the context of a complete system. Thiscan become a serious problem as more of these power aware systems are beingdeployed in mission critical applications.To address the problem of technique integration for power-aware embedded systems, we propose a new design tool framework called IMPACCT and the associated design methodology. The system modeling methodology includes application model for capturing timing/powerconstraints and mode dependencies at the system level. The tool performs power-awarescheduling and mode selection to ensure that all timing/power constraintsare satisfied and that all overhead is taken into account. IMPACCT then synthesizesthe implementation targeting a symmetric multiprocessor platform. Experimentalresults show that the increased dynamic range of power/performance settingsenabled a Mars rover to achieve significant acceleration while using lessenergy. More importantly, our tool correctly combines the state-of-the-arttechniques at the system level, thereby saving even experienced designersfrom many pitfalls of system-level power management. 相似文献
60.
本文提出一种关于DMT系统传输纯数据流业务的最佳的功率分配算法,该算法使用了一种有效的表格查手工艺工和拉格朗日乘法器对分搜索办法,能够较快的收敛到最佳的功率点。同时,易于用硬件和软件实现。 相似文献