绝对时钟智能控制器的研制

介绍了一种日常参数智能控制器的研制及研制过程中的几个重要问题的解决方法。特别是用于城市照明及美化城市的彩灯的开、关时间智能控制方面，给出了依据当地绝对时间、经度、纬度进行昼夜时间计算的方法，使之在不接光电传感器情况下可跟踪季节的昼夜变化。控制系统采用８９Ｃ２０５１单片机，配有时钟日历芯片ＤＳ１２８８７，系统体积小、功能强、可靠性高。     

DGPSL：A DISTRIBUTED GRAPHICS LIBRARY

ＤＧＰＳＬ：ＡＤＩＳＴＲＩＢＵＴＥＤＧＲＡＰＨＩＣＳＬＩＢＲＡＲＹＳｈｉＪｉａｏｙｉｎｇ；ＰａｎＺｈｉｇｅｎｇ；ＺｈｅｎｇＷｅｎｔｉｎｇＤＧＰＳＬ：ＡＤＩＳＴＲＩＢＵＴＥＤＧＲＡＰＨＩＣＳＬＩＢＲＡＲＹ￥ＳｈｉＪｉａｏｙｉｎｇ；ＰａｎＺｈｉｇｅｎｇ；...     

银河－Ⅱ气象应用并行库

本文着重介绍“银河－Ⅱ气象应用并行库”的设计思想、技术特点和使用方法。     

Efficient Parallel Algorithms for Some Graph Theory Problems

In this paper,a sequential algorithm computing the aww vertex pair distance matrix D and the path matrix Pis given.On a PRAM EREW model with p,1≤p≤n^2,processors,a parallel version of the sequential algorithm is shown.This method can also be used to get a parallel algorithm to compute transitive closure array A^* of an undirected graph.The time complexity of the parallel algorithm is O(n^3/p).If D,P and A^* are known,it is shown that the problems to find all connected components,to compute the diameter of an undirected graph,to determine the center of a directed graph and to search for a directed cycle with the minimum(maximum)length in a directed graph can all be solved in O(n^2/p logp)time.     

大功率UPS的并联控制技术

提出了一种新的N 1三相大功率UPS的并联控制方案，并且在4台40KVA三相在线式UPS上进行了实验研究，实际运行结果证明采用此方法可以获得良好的静态与动态特性。     

逆变电源并联技术

逆变器并联是提高电源系统可靠性 ,扩充系统容量的有效方式。本文介绍了逆变电源并联的原理、技术要求和特点。对当前采用的逆变电源并联方案进行了总结和分类。在此基础上详细分析了各种并联方案的特点和内在关系 ,指出了逆变电源并联技术的发展趋势。     

集群计算机上基于BSP模型的并行算法及其程序设计

文章分析了BSP模型和集群计算机的特点，给出了在集群计算机根据BSP模型设计并行算法及其软件的原则，举例说明了利用BSP模型代价公式定性分析并行算法性能的方法，并利用实验结果验证了得出的结论。结果表明模型的成功地抽象出了集群计算中影响算法性能的诸种因素，并通过代价公式反映出来，利用代价公式可以基本准确地估计并行算法代价，这对集群计算机上的并行算法及其软件及设计和优化具有重要的指导意义。     

Parallel path consistency

Filtering algorithms are well accepted as a means of speeding up the solution of the consistent labeling problem (CLP). Despite the fact that path consistency does a better job of filtering than arc consistency, AC is still the preferred technique because it has a much lower time complexity. We are implementing parallel path consistency algorithms on multiprocessors and comparing their performance to the best sequential and parallel arc consistency algorithms.^(1,2) (See also work by Kerethoet al. ⁽³⁾ and Kasif⁽⁴⁾) Preliminary work has shown linear performance increases for parallelized path consistency and also shown that in many cases performance is significantly better than the theoretical worst case. These two results lead us to believe that parallel path consistency may be a superior filtering technique. Finally, we have implemented path consistency as an outer product computation and have obtained good results (e.g., linear speedup on a 64K-node Connection Machine 2).     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.