Scheduling in or-parallel Prolog systems: Survey and open problems

Implementation of or-parallel Prolog systems offers a number of interesting scheduling problems. The main issues are the interaction between memory models and scheduling, ordering of multiple solutions, and scheduling of speculative work. The problems occur partly because of the design choices (e.g. the choice of a memory model), and partly because of the desire to maintain observational equivalence between parallel and sequential implementations of Prolog, while achieving high efficiency. In the first part of this paper a common framework for discussing scheduling in or-parallel systems is introduced, and also a collection of issues that must be addressed in such systems is presented. In the second part of the paper we survey a number of solutions to these problems comparing their efficiency whenever possible. We close the survey with a short discussion of open problems.Current association: Carlstedt Elektronik AB     

On Striping Traffic over Multiple IEEE 802.11(b) Wireless Channels

Due to interference, path loss, multipath fading, background noise, and many other factors, wireless communication normally cannot provide a wireless link with both a high data rate and a long transmission range. To address this problem, striping network traffic in parallel over multiple lower-data-rate but longer-transmission-range wireless channels may be used. In this paper, we propose a new striping method and evaluate its performances over multiple IEEE 802.11(b) channels under various conditions. Our extensive simulation results show that this method is quite effective for such an application. S.Y. Wang is an Associate Professor of the Department of Computer Science and Information Engineering at National Chiao Tung University, Taiwan. He received his Master and Ph.D. degree in computer science from Harvard University in 1997 and 1999, respectively. His research interests include wireless networks, Internet technologies, network simulations, and operating systems. He is the author of the NCTUns 2.0 network simulator and emulator, which is being widely used by network and communication researchers. More information about the tool is available at http://NSL.csie.nctu.edu.tw/nctuns.html. C.H. Hwang received his master degree in computer science from NCTU in 2002 and currently is working for a network company. C.L. Chou currently is a third-year Ph.D. student at the Department of Computer Science and Information Engineering, National Chiao TungUniversity (NCTU), Taiwan. He received his master degree in computer science from NCTU in 2002.     

一种抗干扰能力极强的计算机通信接口电路

设计了一种结构简单，抗干扰能力极强的计算机通信接口电路。该电路利用模拟开关实现了全数字二态电平（1，0）与三态电平(1，0，-1)之间的相互转换；利用模拟开关导通电阻的动态效应以及MOS晶体管开启电压Vτ的衬偏效应，提高了接收电路的抗干扰能力，提出了一种与共模干扰无关的模拟数字混合接收电路。     

EDA实现的PLD遥控解码电路

介绍了电子设计自动化EDA (ElectricalDesignAutomation)技术的基本特点 ,以红外遥控为例 ,提出了一种PLD (可编程逻辑器件 )解码电路 ,并用ispLSI10 6 0实现 ,该电路原理简单、设计方便、工作可靠 ,可用于以键盘扫描为输入方式的智能仪器中。     

一种快速CRC 算法①的硬件实现方法

介绍了CRC校验算法的硬件电路实现方法。CRC校验广泛应用于通信、存储系统，在串行CRC实现的基础上，对电路结构提出了改进的方案，并实现了CRC的并行计算，由此进一步可以适用于任意位数据宽度的数据输入情况。     

可编程光学二值双轨逻辑门

基于双轨逻辑,本文提出一种可级联的并行二值逻辑门。所有十六种二值逻辑运算可以采用偏振半波相延编程来实现。也提出了用电光晶体实现实时编程的方法。本文中给出了实验结果。     

8098单片机在单相调压器中的应用

将8098单片机所特有的用软件来实现A/D,D/A及PWM信号输出的特性应用在模拟式移相电路中,展示了模拟式移相电路改造成具有智能化特点的一条有效途径。     

时序电路逻辑初始化问题研究

讨论同步时序电路初始化问题,提出了一种基于电路存储元件逻辑定级和可控性分析的同步时序电路逻辑初始化方法。同时也给出了针对ISCAS89电路的一些实验结果。     

正交多项式的并行算法修正及其稳定性分析

通过修正求解Chebyshev多项式的Clenshaw和Forsythe算法。提出了求解一般正交多项式的两种并行算法。并通过讨论这两种并行算法矩阵形式的舍入误差，对它们的稳定性进行了分析。     

DLL23XA双侧向测井仪的研制

以往双侧向测井仪动态范围小，测量精度低，为此开发了DLL23XA双侧向测井仪。该仪器主要单元采用厚膜电路，稳定性、一致性好；深、浅屏流源采用可变功率控制，提高了仪器的动态范围。仪器采用3506P例进行数据传输，可方便地配接各种地面系统。