STI process steps for sub-quarter micron CMOS

This paper presents Shallow Trench Isolation (STI) process steps for sub-1/4 μ CMOS technologies. Dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection, have been used for a 0.18 μm CMOS technology. Electrical results obtained with a 5.5 nm gate oxide thickness show good isolation down to 0.3 μm spacing. Good transistor performances have been demonstrated.     

CMOS电路中抗Latch-up的保护环结构研究

闩锁是CMOS集成电路中的一种寄生效应,这种PNPN结构一旦被触发,从电源到地会产生大电流,导致整个芯片的失效。针对芯片在实际测试中发现的闩锁问题,介绍了闩锁的测试方法,并且利用软件Tsuprem4和Medici模拟整个失效过程,在对2类保护环(多子环/少子环)作用的分析,以及各种保护结构的模拟基础之上,通过对比触发电压和电流,得到一种最优的抗Latch up版图设计方法,通过进一步的流片、测试,解决了芯片中的闩锁失效问题,验证了这种结构的有效性。     

PRO——一种新的地震资料处理方法

PRO(影像的参数展开)技术是由俄罗斯地球物理学家开发的一种崭新的地震资料处理技术。本文从PRO基本原理入手,简单介绍了PRO的速度分析原理。PRO速度分析和成像均以信号的椭圆展开和参数展开为基础,其中参数展开方法考虑波型转换、介质的横向不均匀造成传播速度的变化。该技术抛开了传统共中心点叠加的思想,从根本上解决了以CMP方法为基础的传统地震处理技术遇到的困难。通过模型与实例分析对比,PRO比传统CMP方法更优越。     

斜拉桥动力特性的参数分析

建立了斜拉桥动力分析的三维有限单元模型 ,研究了单元类型和参数变化对斜拉桥动力特性的影响。详细地讨论了斜拉桥非线性来源 ,并运用 6节点薄壁单元和 4节点索单元分别考虑了斜拉桥弯曲构件和索的非线性特性。通过对一斜拉桥的数值分析 ,得到了关于斜拉桥动力参数敏感性的一般结论。     

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.     

Lowpass and bandpass transadmittance filter using operational amplifier pole

A new topology simultaneously implementing lowpass (LP) and bandpass (BP) transadmittance filtering signals using a single operational amplifier (OA), one capacitor, and two resistors is presented. The input impedance is very high which is essential for cascading without employment of buffers. The circuit uses absolute minimum number of active and passive components. The filter employs pole-model of OA and as such has acquired suitability for extended frequency operation. The circuit permits separate adjustment of natural frequency (ω₀) and quality factor (Q) in an orthogonal manner. The circuit has low sensitivity figures unlike the reported single amplifier biquads. The PSPICE simulation results are included.     

Monte-Carlo Simulation of Clocked and Non-Clocked QCA Architectures

We present a Monte Carlo simulation of two implementations of Quantum Cellular Automaton (QCA) circuits: one based on simple ground state relaxation and the other on the clocked cell scheme that has recently been proposed by Tóth and Lent. We focus on the time-dependent behavior of two basic circuits, a binary wire and a majority voting gate, and assess their maximum operating speed and temperature requirements for different sets of fabrication parameters.     

On the Realization of Current－Mode Continuous－Time Operational Transconductance Capacitance Filter

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矢量图的参数化重建系统——VACAD

本文重点探讨了如何将矢量图形进行参数化重建，即从只具备纯几何信息的矢量图中抽取元素间的拓扑信息，从而保证尺寸变动时保持拓扑关系不变，并能对多视图进行同步处理。这一方法的最大优点是用户作图时不受约束，因为系统只处理最终图形。另外，该思想并不局限于Ａｕｔｏ ＣＡＤ环境上，可方便地推广到其它二维绘图系统中。     

Low-Power Adaptive Biased Integrated Amplifiers

In this paper the author will present the working principle and the applications of a novel adaptive biasing topology, designed to decrease the stand-by power dissipation without affecting the transient performance of low-power amplifiers. The proposed circuit, whose principle and circuit topology can be implemented both in CMOS and in bipolar standard technologies, gives a biasing current whose value depends on the applied input differential voltage and can be set according to the requested transient performance constraints. The adaptive architecture can be utilized in the design of high-efficient low-power operational amplifiers, for the biasing of both the input stage (where the input source current is dynamically increased) and the output stage (where the output current can be controlled and limited). These amplifiers show a very good behaviour, evaluated in terms of two efficiency factors, if compared with those of other adaptive solutions and class-AB topologies, proposed in the literature. Simulation results and also measurements on a chip prototype, fabricated in a standard CMOS technology, are finally presented.