Analytical investigation and parametric study of lateral impact behavior of pressurized pipelines and influence of internal pressure

This article provides a combined computational and analytical study to investigate the lateral impact behavior of pressurized pipelines and inspect all the parameters such as the outside diameter and internal pressure and evaluate how they affect such behavior. In this study, quartic polynomial functions are applied to formulate the maximum crushing force (F_max), maximum permanent displacement (W), and absorbed energy (E) of the pressurized pipelines during the impact problem. The effects of the diameter and pressure on F_max, W, and E are therefore illustrated through analyzing these functions. Response surfaces are also plotted based on the generated quartic polynomial functions and the quality (accuracy) of these functions are verified through several techniques.     

X80管线钢在含硫酸盐还原菌的土壤环境中的应力腐蚀开裂行为研究进展

X80管线钢因具有高强度、高韧性、抗脆断等性能,已成为现代油气运输中应用最为广泛的钢材之一。X80管线钢在埋地土壤环境中不可避免地受到应力和SRB(Sulfate-reducing bacteria)的共同作用,近年来有关X80管线钢在含SRB的土壤环境中的应力腐蚀开裂已成为一个研究重点。综述了应力腐蚀开裂和SRB腐蚀的影响因素,总结了关于应力和SRB协同作用对X80管线钢腐蚀行为影响的研究现状,分析了现行研究的缺陷和不足,并针对这些问题对今后的研究进行了展望。     

挠性软管在渤海海底管道的应用

本文结合在渤海海底管道工程中应用挠性软管的实践,论述了挠性软管的几个主要技术问题,如挠性软管的结构和材料特性,不同输送介质条件对挠性软管结构和材料的影响,挠性软管与普通钢管的连接方式以及运输、安装等方面的一般要求。此外,还探讨了挠性软管在渤海海底管道工程中可以应用的几个方面。     

流水线前端资源分配及其性能影响研究

动态超标量处理器的性能取决于流水线各段资源的配置情况,通常认为资源越多对性能提升越有利。对流水线前端资源的分配进行研究,发现各类资源的合理搭配更重要,资源配置过多或搭配不当可能产生负面影响。分析各类资源的潜在互相干扰、影响性能的现象、过程及深层次原因,并给出一些参考建议。     

并行图形绘制技术综述

为研究并行图形绘制技术,介绍图形绘制的流水线过程,对其内在的可并行性进行分析,研究并行绘制的实现方式,包括流水线并行、数据并行和作业并行,以及前分布拼接合成、中分布拼接合成和后分布拼接合成,讨论并行绘制面临的主要问题及其发展趋势。     

检测石油管道冰堵与定位的光纤传感器的研究

寒冷地区成品油管道冰堵现象时有发生.利用分布式光纤传感器检测管道沿途发生的冰堵信息;利用具有表征信号局部特征能力韵小波分析的方法确定光纤两端2个测试信号的时延,进而即可确定冰堵点的位置.阐述了其测试原理和堵塞点定位方法,理论分析和仿真实验结果表明:该方法可以有效提高管道冰堵测试的灵敏度和定位精度.     

基于神经网络的变流量管路摩阻系数计算

应用改进的BP神经网络算法对过渡区内流量变化下的蒸汽管路摩阻系数进行了预测,解决了因蒸汽流量变化而使得摩阻系数值计算过程复杂繁琐、效率低下的问题。实例表明,该方法得到的仿真值与Colebrook方程计算值符合较好,所产生的误差平均水平能够满足工程计算的精度要求。     

FPGA implementation and performance evaluation of a high throughput crypto coprocessor

This paper describes the FPGA implementation of FastCrypto, which extends a general-purpose processor with a crypto coprocessor for encrypting/decrypting data. Moreover, it studies the trade-offs between FastCrypto performance and design parameters, including the number of stages per round, the number of parallel Advance Encryption Standard (AES) pipelines, and the size of the queues. Besides, it shows the effect of memory latency on the FastCrypto performance. FastCrypto is implemented with VHDL programming language on Xilinx Virtex V FPGA. A throughput of 222 Gb/s at 444 MHz can be achieved on four parallel AES pipelines. To reduce the power consumption, the frequency of four parallel AES pipelines is reduced to 100 MHz while the other components are running at 400 MHz. In this case, our results show a FastCrypto performance of 61.725 bits per clock cycle (b/cc) when 128-bit single-port L2 cache memory is used. However, increasing the memory bus width to 256-bit or using 128-bit dual-port memory, improves the performance to 112.5 b/cc (45 Gb/s at 400 MHz), which represents 88% of the ideal performance (128 b/cc).     

Sense and sidedness in the graphics pipeline via a passage through a separable space

Computer graphics is ostensibly based on projective geometry. The graphics pipeline—the sequence of functions applied to 3D geometric primitives to determine a 2D image—is described in the graphics literature as taking the primitives from Euclidean to projective space, and then back to Euclidean space. This is a weak foundation for computer graphics. An instructor is at a loss: one day entering the classroom and invoking the established and venerable theory of projective geometry while asserting that projective spaces are not separable, and then entering the classroom the following week to tell the students that the standard graphics pipeline performs clipping not in Euclidean, but in projective space—precisely the operation (deciding sidedness, which depends on separability) that was deemed nonsensical. But there is no need to present Blinn and Newell’s algorithm (Comput. Graph. 12, 245–251, 1978; Commun. ACM 17, 32–42, 1974)—the crucial clipping step in the graphics pipeline and, perhaps, the most original knowledge a student learns in a fourth-year computer graphics class—as a clever trick that just works. Jorge Stolfi described in 1991 oriented projective geometry. By declaring the two vectors and distinct, Blinn and Newell were already unknowingly working in oriented projective space. This paper presents the graphics pipeline on this stronger foundation.

异步128位AES算法的硬件设计

基于四相握手协议设计异步流水线,实现单轮运算内流水操作,设计轮运算启动模块和异步控制信号生成模块,满足算法多轮运算的需要。在子密钥生成模块、字节替代模块和列混合模块使用复用技术,降低了对硬件的需求。在COMS0.18μm工艺下进行综合、布局布线和仿真,与采用同样数据路径设计方法的同步电路相比,吞吐率提高了12.5%。