基于VHDL的CCD驱动时序设计

本文介绍了使用一种标准的硬件描述语言VHDL编写CCD驱动电路的新方法，给出了时序仿真波形，并验证了其可行性。     

0. 6 􀀁m CMOS 雷达天线专用控制芯片设计

雷达系统中天线控制电路完成上位机的初始化和扫描角度控制,要求具有高可靠性和低静态电流,用专用集成电路进行设计具有明显优势.采用Verilog HDL语言描述了系统的逻辑功能,超前进位结构的加/减法器提高了电路的工作速度.利用0.6 μm CMOS工艺完成了天线控制电路的物理实现,芯片面积为1.695 mm×1.631 mm.     

A Compositional Framework for Hardware/Software Co-Design

We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derivefrom a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory.     

基于虚拟可重构平台的时序电路演化设计

目前,电路进化设计是演化硬件研究的主要方向之一。而时序电路由于存在反馈环不便于进行电路描述和软件仿真。文中对时序电路的演化设计方法进行了改进,提出了专门针对时序电路演化的虚拟可重构平台,建立起电路编码与HDL代码的映射关系。应用TEXTIO和MATLAB来辅助仿真测试过程,使测试向量数量巨大、难以处理的问题得到很好地解决。最后调用ModelSim完成了FSM的演化实验。实验结果验证了基于此平台演化时序电路的可行性和有效性。     

基于AMBA总线的IIC协议IP核设计与验证

介绍了一种基于AMBA总线verilogHDL实现的IIC主机模式的IP核设计。该模块能够在标准和快速模式下运行,能够灵活配置为十位地址寻址或七位地址寻址模式。详细说明了该IP核的架构,各部分设计及状态转换过程。最后该模块通过了系统验证,并在xilinxFPGA上转化为硬件电路实现了所有功能。     

数字可控正弦信号发生器的设计

该文采用DDS架构设计了可控正弦信号的产生方法。首先分析了数字可控正弦信号的基本原理;其次,采用Verilog HDL语言进行编程,在FPGA平台上进行了仿真及板级调试;最后,在示波器上得到了正确波形。该成果可用作一般信号处理过程的信号发生器,具有科学、准确、易实现,灵活及便携等优点。     

一种时序型总线硬件木马的植入与检测

RS总线集成电路在航空航天及工业控制领域具有广泛的应用,随着集成电路硬件木马的检测成为研究热点,作为总线硬件木马研究领域的分支,其设计越来越受关注。在常规时序型硬件木马的基础上,针对RS232总线集成电路,设计一种基于可逆计数器的时序型总线硬件木马。采用Xillix公司的ISE软件在RTL层设计相应的RS232总线Verilog代码,并在常规和可逆时序型硬件木马触发阈值呈等差递增的条件下进行Modelsim仿真分析,结果表明,在总线功能需求复杂和传输数据较多的情况下,可逆时序型木马比常规时序型硬件木马具有灵活性和较低的触发率,隐蔽性更强。     

Mass spectrometric immunoassay and MRM as targeted MS-based quantitative approaches in biomarker development: Potential applications to cardiovascular disease and diabetes

Type 2 diabetes mellitus (T2DM) is an important risk factor for cardiovascular disease (CVD)—the leading cause of death in the United States. Yet not all subjects with T2DM are at equal risk for CVD complications; the challenge lies in identifying those at greatest risk. Therapies directed toward treating conventional risk factors have failed to significantly reduce this residual risk in T2DM patients. Thus newer targets and markers are needed for the development and testing of novel therapies. Herein we review two complementary MS-based approaches—mass spectrometric immunoassay (MSIA) and MS/MS as MRM—for the analysis of plasma proteins and PTMs of relevance to T2DM and CVD. Together, these complementary approaches allow for high-throughput monitoring of many PTMs and the absolute quantification of proteins near the low picomolar range. In this review article, we discuss the clinical relevance of the high density lipoprotein (HDL) proteome and Apolipoprotein A-I PTMs to T2DM and CVD as well as provide illustrative MSIA and MRM data on HDL proteins from T2DM patients to provide examples of how these MS approaches can be applied to gain new insight regarding cardiovascular risk factors. Also discussed are the reproducibility, interpretation, and limitations of each technique with an emphasis on their capacities to facilitate the translation of new biomarkers into clinical practice.     

VCPPS:一种面向并行Verilog模拟的代码分割器

本文介绍了一种面向并行模拟的Verilog代码分割器VCPPS。VCPPS通过图形化的方式进行人机交互,并采取用户启发式的方法指导分割。文章介绍了VCPPS设计与实现中的一些关键技术,通过分析可以看出,VCPPS可以正确地完成繁琐的Verilog代码分割工作,为并行Verilog模拟提供支持。     

基于FPGA的偶数分频器设计

随着电子技术的发展,工作频率成为电子产品优劣的一个重要依据,这使得我们对晶振的要求越来越高。如果我们仅通过分频,对较高的晶振源进行分频就能很容易的得到比较丰富的频率。分频器是数字系统设计中的一种基本电路,本文介绍了通过QuartusII开发平台,利用Verilog硬件描述语言设计了一种能够实现等占空比的任意偶数分频、等占空比任意奇数分频、不等占空比的任意半整数分频的较为通用的分频器,并通过QuartusII进行了功能仿真。