基于状态翻转连续长度码的测试数据压缩和解压

提出了新一类的变-变长度压缩码，称之为状态翻转连续长度码。该文在测试序列中直接编码连续的“0”和“1”的长度，压缩一个预先计算的测试集，无需像其它文章中受限制仅仅编码连续的“0”，又解决了交替-连续长度码中对两个相邻的连续序列进行编码时必须附加一位的问题。该方法的解压结构是一个简单的有限状态机，不需要一个与扫描链等长的循环扫描移位寄存器。实验结果表明，这种编码能够有效地压缩测试数据。     

基于极大自正交码的S-链构造

研究了码长n满足11≤n≤19的二元不可分解极大自正交码的对偶距离最优或拟最优的子码,以及由对偶距离最优或拟最优自正交码构造出的S-链,应用所得到的S-链构造出一些较好的量子纠错码。     

MIMO系统中一种低复杂度联合检测算法

本文改进了概率数据辅助(probabilistic data association,PDA)算法,将其应用于MIMO(multiple-input multi- ple-output)系统中,并提出了一种partial-PDA LDPC联合检测算法,比PDA LDPC联合检测算法的计算复杂度更低。计算机仿真结果显示,partial-PDA LDPC联合检测算法能够取得非常接近于PDA LDPC联合检测算法的系统性能。     

性能接近最优的LDPC码LLR-BP简化译码算法

讨论了LDPC码的LLR-BP译码算法,对多项式拟合和偏移量近似两种简化算法进行了研究,通过仿真的方法确定了近似参数;算法仿真结果表明,这两种简化算法不仅易于硬件实现,而且性能接近最优。     

一种改进的二阶Reed-Muller译码算法

研究了一种改进的RM译码算法—改进的Sidel,nikov-Pershakov算法(简称SP算法),详细叙述了原始算法的原理以及改进算法的译码步骤,并对两种算法进行了仿真实现,对它们的译码性能和算法复杂度进行了比较。改进的译码算法复杂度略优于原始算法,而改进后的算法的译码性能明显优于原始算法。     

DVB-S2中IRA码EXIT曲线图分析方法研究

基于IRA码迭代译码器结构，丈中研究了EXIT曲线图性能分析方法。利用此方法求出DVB—S2中各种码率IRA码的收敛门限值，并与高斯近似和密度进化方法求得的结果进行比较分析，探讨了EXIT曲线图的优点和应用技术。     

提高检突发错误能力的LDPC码的构造方法

当前LDPC码的构造方法都是偏重于提高码的性能、降低编码复杂度2个方面，没有考虑码组之间的汉明距离和汉明距离分布，从而漏检部分突发错误。给出了一种次优的考虑码组汉明距离分布的构造方法，和已有的方法相比，这种方法构造的LDPC码不仅可以检突发长度小于校验矩阵秩的突发错误，并且保持纠随机错误性能不变。     

High Data Rate Alamouti Code From Field Extension

Alamouti code is the only known Orthogonal Space Time Block Code (OSTBC) with rate-1. All other known orthogonal codes have rate less than unity. The orthogonal property of OSTBCs reduces the decoding complexity to a large extent. High data rate Space Time Block Codes for arbitrary number of transmit antennas were recently proposed based on Division Algebras. But these STBCs are not orthogonal. Therefore their decoding complexity is very high. In this paper we propose high data rate Alamouti codes from field extensions for two transmit antennas. Our codes have better coding gain than the both high rate codes from division algebra and the rate-1 Alamouti code. Vishwanath R was born in Hyderabad, India in 1982. He did his B.E. in Electronics and Communications Engineering from Birla Institute Of Technology, Ranchi, India in 2002 and Master of Technology in Communications Engineering in 2005 from Indian Institute of Technology Delhi, India.. Currently he is pursuing PhD from Indian Institute of Technology Delhi, India. His research interests include Routing in Optical Networks, Signal Processing, Wireless Communications and Image Processing. He is a member of the IEEE. Bhatnagar Manav R was born in Moradabad, India in 1976. He did his B.E. in Electronics in 1997 and Master of Technology in Communications Engineering in 2005 from Indian Institute of Technology Delhi, India. He has worked as lecturer in Moradabad Institute of Technology, Moradabad, India from 1998–2003. He is currently pursuing PhD from Indian Institute of Technology Delhi, India. His research interests include Routing in Optical Networks, Signal Processing in Wireless Communications and Image Processing. He is a member of the IEEE.     

Reconfigurable Antenna for Future Wireless Communication Systems

This paper deals with the processing techniques which are known as reconfigurable antennas: these methods are foreseen to be a booster for the future high rate wireless communications, both for the benefits in terms of performance and for the capacity gains. In particular, adaptive digital signal processing can provide improved performance for the desired signal in terms of error probability or signal-to-noise ratio while the bandwidth efficiency can be increased linearly with the number of transmitting and receiving antennas. In this article, the main antenna processing techniques are reviewed and described, aiming at highlighting performance/complexity trade-offs and how they could be implemented in the future systems. The coexistence of all these different technologies in a wireless environment requires high efficiency and flexibility of the transceiver. Future transceiver implementations which are based on the Software Defined Radio technology are also reviewed and described.     

空间存储器纠错系统的软件实现

本文分析了国际空间站AMS存储系统中一些恶劣的空间环境对随机存储器RAM电路的影响,它可能改变半导体记忆器件的逻辑状态,导致存储单元在逻辑"0"与"1"之间发生翻转等问题.本文采用了基于纠错编码基本原理的BCH(15,7)算法,该算法能够有效解决两位随机错误的纠正问题.本文采用错误图样查找的译码方法,用Verilog DHL来设计BCH(15,7)码的编码与解码,并下载到FPGA芯片上,通过仿真和实践都证明了这种方案的正确性和可行性.