基于单元故障模型的树型加法器的测试

首先分析了树型加法器的原理，总结了其运算特性．其次在介绍单元故障模型的基础上分析了树型加法器的测试向量生成．分析结果表明，5n-1个测试向量可以实现树型加法器中所有单元故障的检测．这些测试向量具有很好的规则性，能够利用片上测试向量生成器实现，适合于应用内建自测试技术测试．基于此，作者提出了一种内建自测试的测试结构，测试时只需存储7个籽测试向量，其它测试向量可以在这7个籽测试向量的基础上通过循环移位实现．最后给出了实验分析结果．     

组合电路可测试性技术的研究

随着集成电路设计规模的不断增大,在芯片中特别是系统芯片SOC(system on a chip)中组合电路的可测试性设计方法变得越来越重要.本文采用内建自测试技术对组合电路进行可测试性设计.文中详细分析了组合电路内建自测试的实现原理,通过将测试生成及响应分析逻辑置入电路内部,提高了电路的可控制性和可观察性,从而可使该电路的测试和诊断快速而有效.最后对8位行波进位加法器的内建自测试设计过程进行了详细分析,并通过MAX plusⅡ进行了实现.     

用于SOC测试的一种有效的BIST方法

为了提高SOC芯片的可测性和可靠性,我们提出了一种SOC测试的BIST技术的实现方案.针对某所自行研制的数字模拟混合信号SOC芯片,我们使用了不同的可测性技术.比如对模拟模块使用改进的BIST方法,对嵌入式存储器使用了MBIST技术.一系列的测试实验数据表明,该BIST方法能有效提高测试覆盖率.     

BISTing Datapaths under Heterogeneous Test Schemes

In this paper, we present a fast and efficient algorithm for BISTing datapaths described at the Register Transfer (RT) level. This algorithm is parameterized by user defined tuning factors allowing tradeoffs between fault coverage, area overhead and test application time. This algorithm is generic in the sense it handle and mixes heterogeneous test pattern generators and compactors.     

Investigations for Minimum Invasion Digital Only Built-In “Ramp” Based Test Techniques for Charge Pump PLL's

Due to a number of desirable operational and design characteristics, CP-PLL's (Charge Pump Phase locked loops) have, in recent years become a pervasive PLL architecture. CP-PLL architectures are exploited for a variety of applications such as on chip clock generation, CRC (clock recovery circuits) and Radio frequency synthesis applications. This paper describes a simple, digital only, minimally invasive and fully automated test approach for high performance CP-PLL's that can be used to provide more information about the CP-PLL function beyond that obtained through the commonly used FLT (Frequency Lock Test). The test strategy described here allows the estimation of forward path (FP) gain and relative leakage in the forward path loop components. Applications of the test are focussed towards digital only testing of fully embedded CP-PLL's, however further test modifications could yield marked test time improvements for embedded and board level CP-PLL's incorporating multiple CP currents and or multiple loop filter (LF) configurations.     

On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level

Test power requirements for complex components are becoming stringent. The purpose of this paper is to reuse a recently proposed RT (Register Transfer) Level test preparation methodology to drive innovative Low-Energy (LE)/Low-Power (LP) BIST solutions for digital SoC (System on a Chip) embedded cores. RTL test generation is carried out through the definition of a reduced set of partially specified input vectors (masks), leading to a high correlation between multiple detection of RTL faults and single detection of likely physical defects. The methodology is referred as masked-based BIST, or m-BIST. BIST quality is evaluated considering three attributes: test effectiveness (TE), test length (TL) and test power (TP). LE BIST sessions are defined as short test sequences leading to high values of RT-level IFMB metrics and low-level Defects Coverage (DC). The energy and power of the BIST sessions, with and without mask forcing, is computed. It is shown that, by forcing vectors with the RTL masks, short BIST sessions, with low energy and with a comparable (or smaller) average power consumption, as compared to pseudo-random test, are derived. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and modules of the CMUDSP and TORCH ITC'99 benchmark circuits.     

用于跳变故障测试的确定性逻辑内建自测试方法

BIST由于支持全速测试而成为延迟故障测试中引人关注的技术.确定性逻辑BIST(DLBIST)已成功应用于固定故障的测试中.由于DF的随机可测试性低于固定故障,故需要对DLBIST方法进行修改.DF测试需要测试向量对,因而与SAF相比,需要更多的映射与逻辑开销.本文针对广泛应用的所谓跳变故障模型,提出了用于跳变故障测试的DLBIST扩展方法,使用FJ产生向量对.实验结果表明,使用本文方法可以获得较高的故障测试效率.     

单/双跳变向量插入式低功耗BIST设计方法

提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的内建自测试BIST(built-in self-test)设计方法,该方法在原始线性反馈移位寄存器LFSR(linear feedback shift register)的基础上加入若干逻辑,使测试向量每周期最多产生两次跳变,因而大大降低了被测电路CUT(circuit under test)的功耗。通过对组合电路集ISCAS’85的实验证明,被测电路的总功耗、平均功耗以及峰值功耗都有大幅度的降低。     

系统芯片SOC的BIST测试研究

针对系统芯片SOC测试出现的难题,介绍了几种目前国际上研究较热的内建自测试BIST(Built InSelf Testing)方法,分析了这几种方法的优缺点,并对其作出探讨,最后,展望了系统芯片SOC的BIST发展。     

基于部分相容的动态LFSR重新播种方法

提出了一种基于部分动态LFSR重新播种的改进方法,利用向量的部分相容原理来减少需要编码的确定位的个数,提高数据压缩率。并使用时钟测试来减少生成测试向量所需的时间。实验结果表明,与目前国际同类编码压缩方法相比,该方法提高了编码效率,节约了测试时间。