An on-chip instruction cache design with one-bit tag for low-power embedded systems

On-chip instruction cache is a potential power hungry component in embedded systems due to its large chip area and high access-frequency. Aiming at reducing power consumption of the on-chip cache, we propose a Reduced One-Bit Tag Instruction Cache (ROBTIC), where the cache size is judiciously reduced and the cache tag field only contains the least significant bit of the full-tag. We develop a cache operational control scheme for ROBTIC so that with the one-bit cache tag, the program locality can still be efficiently exploited. For applications where most of the memory accesses are localized, our cache can achieve similar performance as a traditional full-tag cache; however, the power consumption of the cache can be significantly reduced due to the much smaller cache size, narrower tag array (just one bit), and tinier tag comparison circuit being used. Experiments on a set of benchmarks implemented in CMOS 180 nm process technology demonstrate that our proposed design can reduce up to 27.3% dynamic power consumption and 30.9% area of the traditional cache when the cache size is fixed at 32 instructions, which outperforms the existing partial-tag based cache design. With the cache size customization, a further 47.8% power saving can be achieved. Our experimental results also show that when implemented in the deep sub-micron technologies where the leakage power is not ignorable, our design is still efficient - a coherent power saving trend (about 22%) has been observed for technologies from 130 nm down to 65 nm.     

网络课程设计中存在问题及解决策略

网络课程设计思想日趋成熟和完善,在教学实践中得到广泛利用。但网络课程的设计仍存在一些问题。本文从网络课程各个模块的可更新性和各个模块的具体设计分析,提出网络课程存在的一些问题及解决策略。     

基于WEB的网上多媒体教学软件的设计与开发

开发基于WEB的网上多媒体教学软件是实现网络化教学和远程教学(Distance Learning)的资源基础,其优点是不受地域的限制,能够充分利用目前日趋成熟的校园网络,做到资源共享。本文着重介绍了该类教学系统的总体规划和设计思路,以及如何用多媒体著作工具Authorware开发网上教学系统的技巧和方法。     

The learning value of computer-based instruction of early reading skills

Abstract This study examined the unique contribution of computer-based instruction when compared with more conventional modes of instruction (i.e. teacher instruction with textbooks) to early reading skills acquisition, as well as the effects of specific features of computer technology on early reading skills performance. Forty-six pre-school children (aged 5–6), at high risk for learning disabilities, participated in the study. They were assigned to one of three study groups that received different treatments. Three dependent variables were defined, i.e. children's phonological awareness, word recognition and letter recognition skills measured prior and after the treatment. Results clearly indicated that children at high risk who received the reading intervention program with computer materials significantly improved their phonological awareness, word recognition, and letter naming skills relative to their peers who received a reading intervention program with only printed materials and those who received no formal reading intervention program. The results are discussed in detail, with reference to the features of the computer-based materials that contributed to the acquisition of critical early reading skills.     

系统级体系结构仿真器的研究与实现

系统级体系结构仿真器是可以作为一个虚拟目标机器运行的软件系统,它可以实现对单（多）处理器、内存系统、Cache和外部设备等于系统的功能模拟。在体系结构设计和操作系统开发等工程,体系结构仿真器有着广泛的应用。本文介绍了一个基于MISC CPU和SPARC体系结构的系统级仿真器FMCS。     

网络教学交互活动实施现状的调查分析与对策思考

本文通过对网络教学支撑平台交互功能设计的调查、基于典型平台WebCL、Blackboard、Moodle的问卷调查以及BBS论坛样本的内容分析,较为全面、深入地探讨了目前基于网络平台教学交互活动的实施现状与存在的主要问题,并进一步给出了相应的解决对策。     

The cognitive benefits of dynamic representations in the acquisition of spatial navigation skills

A representational theory of the mind suggests that human experiences and activities are underpinned by mental representations. This abstract task representation paradigm may explain a cognitive benefit of dynamic instructional visualisations over static alternative in the acquisition of novel procedural motor skills. In this sequel work, we explore and extend this view through empirical investigations of novel skill acquisitions in a separate but related domain of spatial navigation. We compare the post-learning virtual maze navigational performance of sixty novel learners across two groups. After controlling for spatial orientation ability and prior video gaming experience, participants that learned the task using dynamic instructional visualisations recorded significantly better performance measures than those in the static group. Additionally, within-group comparisons also show that the beneficial advantage of dynamic instructional visualisations over statics remained consistent across different task complexities. These findings provide further evidence to support the view that dynamic instructional visualisations afford more efficient transfer of novel procedural skills through computer based training than static visualisations. This has implications for instructional design especially when rapid novel situational awareness is desired such as in briefings for emergency firefighting or tactical military operations.     

Register swapping schemes for low power execution

For embedded systems, the power dissipation on buses has become an essential issue in recent years. Many real-time embedded processors, such as DSP processors, adopt the Harvard architecture in which the data and instruction buses are separated to avoid processing-speed degradation. The power dissipation on an instruction bus can be reduced if the switching activities between consecutive instructions on that bus are reduced. Two efficient algorithms, the greedy method and the dynamic programming based method, are proposed to swap commutative source register fields of adjacent instructions. The switching activities on the instruction bus are therefore reduced, without affecting the execution results. Experimental results show that the proposed schemes result in a reduction of as much as 21.43% in the switching activities of consecutive source register fields between commutative blocks. In addition, the proposed schemes can be conveniently integrated with other encoding schemes to further improve the power dissipation on an instruction bus.     

Linked instruction caches for enhancing power efficiency of embedded systems

The power consumed by memory systems accounts for 45% of the total power consumed by an embedded system, and the power consumed during a memory access is 10 times higher than during a cache access. Thus, increasing the cache hit rate can effectively reduce the power consumption of the memory system and improve system performance. In this study, we increased the cache hit rate and reduced the cache-access power consumption by developing a new cache architecture known as a single linked cache (SLC) that stores frequently executed instructions. SLC has the features of low power consumption and low access delay, similar to a direct mapping cache, and a high cache hit rate similar to a two way-set associative cache by adding a new link field. In addition, we developed another design known as a multiple linked caches (MLC) to further reduce the power consumption during each cache access and avoid unnecessary cache accesses when the requested data is absent from the cache. In MLC, the linked cache is split into several small linked caches that store frequently executed instructions to reduce the power consumption during each access. To avoid unnecessary cache accesses when a requested instruction is not in the linked caches, the addresses of the frequently executed blocks are recorded in the branch target buffer (BTB). By consulting the BTB, a processor can access the memory to obtain the requested instruction directly if the instruction is not in the cache. In the simulation results, our method performed better than selective compression, traditional cache, and filter cache in terms of the cache hit rate, power consumption, and execution time.     

香港高校信息化建设特点与启示

介绍香港高校在信息化建设及应用方面的特点,并针对性地列举以青岛职业技术学院为代表的高职院校在信息化建设方面存在的不足之处。在对照香港高校信息化对教育发展的推动方面,提出高职院校应该从哪些方面提高,以符合国家在教育信息化方面的举措。