Assessment of local strain field in adhesive layer of an unsymmetrically repaired CFRP panel using digital image correlation

The present study focuses on experimental investigation of through the thickness displacement and strain field in thin adhesive layer in single sided (unsymmetrical) patch repaired CFRP (carbon fiber reinforced polymer) panel under tensile load. Digital image correlation (DIC) technique is employed to acquire the displacement and strain (longitudinal, peel and shear) field. Experimental determination of shear transfer length based on shear strain field obtained from DIC is introduced to estimate the optimum overlap length which is an essential parameter in patch design for the repair of CFRP structures. Further, DIC experiment with magnified optics is performed to get an insight into complex and localized strain field over thin adhesive layer especially at critical zones leading to damage initiation. The failure mechanism, load displacement behavior, damage initiation and propagation are closely monitored using DIC. The influence of patch edge tapering on strain distribution in adhesive layer is also investigated. The DIC successfully captures the global and localized strain field at critical zones over thin adhesive layer and further helps in monitoring the damage based on strain anomalies. Strains are found to have maximum magnitude at the patch overlap edge and the shear strain level in adhesive layer is higher than the peel strain. Normal tapering increases the peel strain and has negligible influence on shear strain level in adhesive layer. The recommended overlap length is found to be consistent with the recommendation in the literature. Whole field strain pattern and the overlap length obtained from experiment are further compared with the finite element analysis results and they appear to be in good coherence.     

Anchoring single Pt atoms on hollow Ag3VO4 spheres for improved activity towards photocatalytic H2 evolution reaction

The high cost of noble metal catalysts has been a great bottleneck for the catalyst industry. Using the noble metal at a single-atom level for catalytic applications could dramatically decrease the cost. The impacts of single Pt atoms on the photocatalytic performance of Ag₃VO₄ have been investigated and reported. In this report, single Pt atoms were anchored on the surface of Ag₃VO₄ (AVO) as a cocatalyst, and the resultant composite photocatalyst has been studied for photocatalytic H₂ production from water driven by visible light. The as-prepared AVO particles are hollow nanospheres in the monoclinic phase with a bandgap of 2.20 eV. The light absorption edge of AVO/Pt is slightly red-shifted compared to that of the pristine AVO, indicating more visible light absorption of AVO/Pt. The XPS peaks of Ag, V, and Pt exhibit a significant shift after AVO and Pt get into contact, suggesting the strong interaction between the surface Ag and V atoms, and single Pt atoms. After 3-h illumination, the photocatalytic H₂ evolution amount from AVO/Pt is improved up to 1400 μmol, which is 2.8 times that on the bare AVO. Such efficient photocatalytic H₂ evolution on AVO/Pt is still maintained after five reaction cycles. The better photocatalytic performance of AVO/Pt has been attributed to the more efficient visible light utilization and the lower interfacial charge transfer resistance, as demonstrated in the DRS and EIS spectra. The presence of the surface Pt atoms also leads to a higher amount of reactive radicals, which could efficiently promote the surface redox reactions.     

Simultaneous accommodation of Dy3+ at the lattice site of β-Ca3(PO4)2 and t-ZrO2 mixtures: Structural stability,mechanical, optical,and magnetic features

Structurally stable β-Ca₃(PO₄)₂/t-ZrO₂ composite mixtures with the aid of Dy³⁺ stabilizer were accomplished at 1500°C. The precursors comprising Ca²⁺, P⁵⁺, Zr⁴⁺, and Dy³⁺ have been varied to obtain five different combinations. The results revealed the fact that complete phase transformation of calcium-deficient apatite to β-Ca₃(PO₄)₂ occurred only at 1300°C, whereas the evidence of t-ZrO₂ crystallization is obvious at 900°C. The dual occupancy of Dy³⁺ at β-Ca₃(PO₄)₂ and t-ZrO₂ structures was evident; however, Dy³⁺ initially prefers to occupy β-Ca₃(PO₄)₂ lattice until its saturation limit and thereafter accommodates at the lattice site of ZrO₂. The typical absorption and emission behavior of Dy³⁺ were noticed in all the systems and, moreover, the surrounding symmetry of Dy³⁺ domains has been determined from the luminescence study. All the systems ensured paramagnetic response that is generally contributed by the presence of Dy³⁺. A gradual increment in the phase content of t-ZrO₂ in the composite mixtures ensured a significant improvement in the hardness and Young's modulus of the investigated compositions.     

面向消费类电子产品的自动化生产线成组技术

针对现代消费类电子产品快速更新换代的现状, 介绍了该类产品的自动化生产线成组技术,阐述了通过度量消费类电子产品相似性和派生性特征,对产线进行成组编码的原理,研究产线工位单元的建模方法,描述了建模内容,并通过有无装载板的产线结构,论述了产线成组编码集成的途径和方法.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

LWIP协议在STLite/OS20操作系统中的移植

介绍了免费的TCP/IP协议栈LWIP开发工具和环境,分析了如何实现LWIP的移植,并给出了一种嵌入式系统与网络互联的新思路。