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61.
电路三要素理论和布尔代数失效原因分析 总被引:9,自引:0,他引:9
本文提出一个克服布尔代数失效的电路三要素理论。文中首先分析布尔代数在数字电路中失效的原因,接着证明开关运算定理等,它概括了文献中曾需一一证明的绝大多数开关运算等式,然后表明:数字电路的统一性既存在于门级和元件级电路间,也存在于各型元件级电路结构间,以及动态与静态电路间。此外,本文提出元件级电路设计的卡诺图方法和代数方法。 相似文献
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《Microelectronics Journal》2014,45(6):734-739
We introduce a novel easy to apply method to detect critical temperature sensitive areas on analog circuits. Our method is based on heat diffusion on a silicon micro-chip: the corners of a temperature sensitive micro-chip are heated up directly by ESD diodes or infrared laser light. This heat stimulus at the corners results in an inhomogeneous temperature distribution. Thus, the temperature is a function in time and space. The elapsed time to change the chip status from “fail” to “pass” as a reaction to the heat stimulus correlates with the distance to the heat source. This correlation is extracted from COMSOL simulations and experimental results. A numerical program based on that correlation succeeded in localization of the temperature sensitive chip module.Micro-chips affected by corner MOSFETs in the subthreshold regime are used to demonstrate our method. 相似文献
63.
《Microelectronics Reliability》2014,54(9-10):1702-1706
The miniaturisation of integrated circuits leads to reliability issues such as electromigration (EMG). This well-known phenomenon is checked at design level by CAD tools. The conventional EMG check methods are based on electrical parameters. However, the wire physical degradation depends also on the interconnection network structure. In order to improve the EMG check methodologies, we propose an accurate method based on failure mechanism and chip power grid configuration. Indeed, the power grid offers redundant paths in case of void in main power supply path. The principle of our method is to take into account the contribution of these redundant paths in power grid lifetime assessment. These effects are validated by silicon ageing tests on structures designed in 28 nm Full Depleted Silicon on Insulator (FDSOI). These accelerated tests results have confirmed the lifetime gain due to the redundancy. These results provide perspectives for the relaxation of wire current limits and improve the chip design toward EMG. 相似文献
64.
《Microelectronics Reliability》2014,54(9-10):2128-2132
Scanning Spreading Resistance Microscopy (SSRM) is successfully applied to investigate failing nLDMOS test devices that exhibit a lowered break down voltage (BVDSS) in electrical test. Cross-sectional, two-dimensional maps of the local sample resistivity from fail and reference (pass) devices reveal significant differences of the dopant concentration in individual, specific regions. This important information enables unambiguous identification of the root cause of the device failure to be dopant related. Furthermore, from a set of hypothesis, which explains the failed electrical test, SSRM results confirm exactly one and rule out the other. These are two important steps towards root cause identification. Since a relative comparison of fail and pass SSRM scans is sufficient for this failure analysis, an extensive data calibration for the absolute dopant concentration by means of additional SSRM measurements on test samples with known dopant concentration is not required. The ability of SSRM to prove or disprove miscellaneous fail hypothesis even without data calibration makes this method a very powerful tool for analysis of dopant related failure types. 相似文献
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通过分析三网融合给电信运营商带来的机遇和挑战,结合电信运营商和广电企业等三网融合主体的优劣势,提出了三网融合背景下电信运营商业务、网络和产业链发展的策略。 相似文献
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介绍了微波低噪声GaAs FET恒定应力加速寿命试验结果,沟道温度T_(ch)为145℃时,平均寿命MTTF为9.64×10~6h,最主要的失效模式是源漏饱和电流I_(DSS)退化降低。建立了表征GaAs FET稳定性的敏感参数I_(DSS)的退化模型InP=a+blnt,分析了I_(DSS)退化与温度应力的加速关系。提出了快速推断器件可靠性的建议。 相似文献
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将线弹簧模型法和响应面法相结合,建立含表面裂纹结构断裂失效概率的计算方法.考虑材料特性、外载荷和裂纹尺寸等参数的不确定性,以含表面裂纹平板为例进行计算,得出失效概率和可靠度指标.与Monte Carlo法结果进行对比,表明该方法合理有效,在大大减小计算量的同时,能够保证很高的精度,适合工程实际应用. 相似文献