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31.
为了满足磁盘存储系统的高数据传输速率和高数据存储密度的需求,造成数字序列之间产生的码间干扰成为接收端获得可靠信息的主要阻碍。本文是以部分响应信号作为离散时间的ISI信道模型,采用基于MAP算法的对数域BCJR(log—MAP)算法进行信道检测。文章介绍了PR信道的模型,对算法的检测原理进行理论分析,并给出几种不同的部分响应信道下的计算机仿真。结果表明该算法能有效地对ISI信道进行检测,能应用于磁记录系统。 相似文献
32.
高压大功率电机在起动时对负载和电网都有比较大的影响。晶闸管串联式高压软起动器以其优越的起动性能和其他一些优点两被广泛使用。本文通过高压软起动器在现场大功率压缩机负载上的应用,分析其工作原理,介绍了起动功能,对晶闸管串联方式的高压软起动做了比较全面的介绍。 相似文献
33.
In this paper, we describe a method for increasing the external efficiency of polymer light‐emitting diodes (LEDs) by coupling out waveguided light with Bragg gratings. We numerically model the waveguide modes in a typical LED structure and demonstrate how optimizing layer thicknesses and reducing waveguide absorption can enhance the grating outcoupling. The gratings were created by a soft‐lithography technique that minimizes changes to the conventional LED structure. Using one‐dimensional and two‐dimensional gratings, we were able to increase the forward‐directed emission by 47 % and 70 %, respectively, and the external quantum efficiency by 15 % and 25 %. 相似文献
34.
A modified soft contact lamination (SCL) process used to fabricate polymer solar cells (PSCs) with nanostructures was developed. Instead of thermally evaporating the metal electrode directly onto the photoactive or the buffer layer, the metal electrode is firstly deposited onto an elastomeric plate made of polydimethylsiloxane (PDMS), then laminated with a substrate coated with conducting polymer via the SCL process, which provides a non-intrusive way to introduce the metal electrode. Since the PDMS plate is compatible for soft lithography, enabling it to be constructed in a light-trapping structure to enhance the power conversion efficiency. Moreover, the architecture of our SCL-fabricated PSCs is suitable for series connecting individual cells to accumulate output voltages for targeting practical applications. 相似文献
35.
《Mechatronics》2015
Tactile display is recently attracting much attention in the field of human–computer interaction. There is a strong need for such a device especially for applications in which the touch feeling is lost, such as surgeons who are willing to feel the tissue hardness during laparoscopic surgeries. In this paper, a novel multi-modal tactile display device which can display both surface shape and stiffness of an object is introduced. The conceptual design is built upon using two springs, made of Shape Memory Alloys (SMA), for displaying shape and stiffness. The design parameters of this device are selected based on the spatial resolution of human finger and the elasticity range of the soft tissue. The display device is simulated using Finite Element Method (FEM) to study the effect of design parameters on the resulting stiffness. Simulation results show that the device can display stiffness of an object independent of its shape display. The experimental setup is built and used for the characterization and control of the SMA springs. Experimental results show that the device can display a stiffness range of (35–110) N/m and elongation up to 5 mm. 相似文献
36.
Soft-error interference is a crucial design challenge in the advanced CMOS VLSI circuit designs. In this paper, we proposed a SEU Isolating DICE latch (Iso-DICE) design by combing the new proposed soft-error isolating technique and the inter-latching technique used in the DICE (Calin et al., 1996 [1]) design. To further enhance SEU-tolerance of DICE design, we keep the storage node pairs having the ability to recover the SEU fault occurring in each other pair but also avoid the storage node to be affected by each other. To mitigate the interference effect between dual storage node pairs, we use the isolation mechanism to resist high energy particle strikes instead of the original interlocking design method. Through isolating the output nodes and the internal circuit nodes, the Iso-DICE latch can possess more superior SEU-tolerance as compared with the DICE design (Calin et al., 1996 [1]). As compared with the FERST design (Fazeli, 2009 [2]) which performs with the same superior SEU-tolerance, the proposed Iso-DICE latch consumes 50% less power with only 45% of power delay product in TSMC 90 nm CMOS technology. Under 22 nm PTM model, the proposed Iso-DICE latch can also perform with 11% power delay product saving as compared with the FERST design (Fazeli, 2009 [2]) that performs with the same superior SEU-tolerance. 相似文献
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为提高GPS/SINS紧耦合系统对于软故障的检测能力,在新息外推法的基础上提出一种历史故障次优融合算法。通过对历史故障进行加权次优融合,形成检验统计量进行故障检测,并提出野值诊断方法,解决该算法易受野值影响的问题。在GPS/SINS紧耦合系统基础上进行对比仿真,结果表明,历史故障次优融合算法在故障量越小的情况下,软故障检测效果越明显,而且能更好地消除野值对故障检测的影响。 相似文献