On frequency response and stability of an optical front–end with variable‐gain current amplifier using a bipolar junction transistor translinear loop

A comparative analysis of implementations of an optical front–end with variable transimpedance intended for optical storage systems in two different BiCMOS technologies is given in this article. The variable‐gain current amplifier within the optical front–end is designed by using a modified balanced type of the bipolar junction transistors translinear loop. The predictions of the optical front–end mathematical models are confirmed by the measured results. They show that a 0.6‐µm BiCMOS silicon technology implementation with worse bipolar junction transistor parameters (unity‐gain frequency, current gain β, and the Early voltage) gives much better stability than a 0.35‐µm BiCMOS silicon‐germanium technology implementation. As a consequence, the useful measured transimpedance dynamic range of the proposed optical front–end is 17.5 times larger in the 0.6‐µm BiCMOS silicon technology than that in the 0.35‐µm BiCMOS silicon‐germanium technology. Copyright © 2012 John Wiley & Sons, Ltd.     

Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers

We present an adaptive frequency compensation technique providing maximum bandwidth closed‐loop amplifiers. The approach exploits an auxiliary variable gain amplifier to implement an electrically tunable compensation capacitor proportional to the feedback factor. In this manner, the closed‐loop bandwidth is kept ideally constant irrespective of the closed‐loop gain. The proposed method can be applied to any amplifier adopting dominant‐pole compensation. As an example, we designed a CMOS amplifier providing 66‐dB direct current gain and 310‐MHz gain‐bandwidth product. For closed‐loop gains ranging from 1 to 10, the closed‐loop bandwidth was found never lower than 401 MHz (noinverting configuration) and 229 MHz (inverting configuration). A similar amplifier with equal gain‐bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed‐loop bandwidth reduced to 33 MHz (noninverting) and 30 MHz (inverting) when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, whereas the other main operational amplifier performance parameters remain almost unchanged compared with the standard solution. Copyright © 2011 John Wiley & Sons, Ltd.     

基于CPLD的缓变微弱电流采集系统设计

针对缓变微弱电流采集的特殊性,本文详细讨论了斩波稳零技术的基本原理,采用高精度斩波稳零型运算放大器TLC2652以及并行接口高速、高精度A/D转换器ADS8811B并采用CPLD实现对其控制,设计了一个基于CPLD的通用高速、高精度、高分辨率、低噪声的缓变微弱电流数字化采集系统.本系统广泛适用于仪器仪表、测控系统及工业现场控制等对微弱缓变电流进行中、高速率采集而且分辨率要求较高的场合.     

正常工作状态与零偏置JFET输入运算放大器的辐射损伤

对处于正常工作和零偏置状态的JFET输入运算放大器,进行了高低剂量率辐射试验。结果表明,工作状态影响JFET运放电路的辐射效应和辐射损伤。正常工作状态下,JFET输入运算放大器表现出时间相关效应,而零偏置状态下则具有低剂量率损伤增强效应。高剂量率或低剂量率辐射情况下,正常工作的JFET输入运放电路参数退化大于或小于零偏置状态。高剂量率辐射会在JFET输入运放的基本单元双极晶体管产生氧化物正电荷和界面陷阱。从氧化物正电荷和界面态与工作状态的关系方面,对JFET运放电路的退化行为进行了解释。     

一种衬底驱动的0.5V全差分运算放大器

为了满足当今对低压低功耗电路的需求,设计了一种工作在0.5V电源电压环境的全差分运算放大器．电路使用了由衬底驱动的输入级和工作在亚阈值区的输出级,并利用交叉耦合输入晶体管的结构产生负跨导来提高增益．采用0.18μm的CMOS工艺,阈值电压约为0.5V的器件模型．Hspice仿真结果表明:直流增益为60dB,单位增益带宽为5.4MHz,功耗为138μW．     

基于多项式的记忆型数字基带预失真器

提出了一种由自适应均衡器和基于多项式的无记忆预失真单元级联组成的记忆型数字基带预失真器．在该预失真器中，首先通过传输窄带训练序列得到能够补偿功率放大器非线性的无记忆预失真器的参数．然后通过一种自适应均衡算法修改均衡器的参数抵消功率放大器的记忆效应．由于将功率放大器的非线性和记忆效应分开处理，其结构和自适应算法复杂度比普通记忆型预失真器大大降低．计算机仿真结果表明，该预失真器能够有效地校正由于功率放大器的非线性和记忆效应引起的信号失真．     

单泵浦光参量放大器增益波长相关性研究

考虑了高阶色散,利用泵浦波、信号波和闲频波耦合方程,推导出了高非线性光纤中信号增益的表达式。该文研究表明光参量放大器的增益与零色散波长附近的泵浦波的波长取值具有相关性。泵浦波波长与零色散波长的值相近时,可以得到较大的增益带宽和较高的增益。当泵浦波波长和零色散波长之差超过一定值时,带宽和增益就会变小。     

新型多功能在线监测系统的硬件部分

介绍了ＺＪ—０１型多功能微机在线监测的硬件部分．该部分由多路转换开关和波形数字采集装置组成，其功能分别是对变电站电气设备的绝缘参数和系统电气参数等信号进行逐一选通、数字采集，送入计算机分析、处理，为绝缘参数和系统电气参数的在线监测提供了保证．该部分电路经优化设计，在性能指标上具有很大的优越性．     

Low‐voltage bulk‐driven input stage with improved transconductance

A low‐voltage input stage constructed from bulk‐driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk‐driven structures. The proposed input stage offers also extended input common‐mode range under low supply voltage in relevant to a gate‐driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common‐mode voltage stabilization and a latch‐up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright © 2010 John Wiley & Sons, Ltd.     

Three‐stage nested‐Miller‐compensated operational amplifiers: Analysis,design, and optimization based on settling time

In analog signal‐processing applications, settling performance of the employed operational amplifiers (opamps) is usually of great matter. Under low‐voltage environment of modern technologies where only a few transistors are allowed to be stacked, three‐stage amplifiers are gaining more interest. Unfortunately, design and optimization of three‐stage opamps based on settling time still suffer from lack of a comprehensive analysis of the settling behavior and closed‐form relations between settling time/error and other parameters. In this paper, a thorough analysis of the settling response of three‐stage nested‐Miller‐compensated opamps, including linear and non‐linear sections, is presented. This analysis leads to a design methodology which determines the circuit requirements for desired settling time/error. Based on settling time, it allows optimizations in power consumption and area. Copyright © 2010 John Wiley & Sons, Ltd.