创建互联网业务价值链

为促进互联网的良性发展,要使设备制造商、电信运营商、虚拟运营商/集团用户、内容提供商和最终用户构成一条互联网业务价值链,价值链的创建对互联网接入设备提出了更高的要求,华为公司的Quid-wayTMA8010Expert多业务综合接入平台可构建宽带城域网分组语音解决方案、可平滑演进为下一代网络中的媒体网关、提供窄带价值链、提供唯一号码业务以及实现多业务综合接入。     

一种实现最佳用户检测的非线性优化神经网络

本文提出并讨论了实现码分多址（CDMA）系统上最佳多用户检测（MUD）的一种神经网络方法。该方法通过将最佳多用户检测视为非线性优化组合问题，利用神经网络能有效求解非线性优化问题的优势，导出了一种非线性优化神经网络来实现最佳多用户检测，理论分析和计算机模拟表明，所提出的神经网络具有可实时应用的动态性能和较传统方法优越得多的误码率性能和抗多址干扰的性能。     

DIRECT RESONANCE OF TURBULENT BOUNDARY LAVER OVER COMPLIANT WALLS

１．　ＩＮＴＲＯＤＵＣＴＩＯＮＴｈｅｍａｉｎｇｏａｌｏｆｔｈｉｓｐａｐｅｒｉｓｔｏｅｘｐｌｏｒｅｔｈｅｐｏｓｓｉｂｉｌｉｔｙｔｏｌｅａｒｎｍｏｒｅａｂｏｕｔｔｈｅｍｅｃｈａｎｉｓｍｏｆｔｕｒｂｕｌｅｎｔｂｏｕｎｄａｒｙｌａｙｅｒｆｌｏｗｉｎｔｅｒａｃｔｉｏｎｓａｎｄｉｔｓｅｆｆｅｃｔｓｏｎｃｏｍｐｌｉａｎｔｗａｌｌｐｅｒｆｏｒｍａｎｃｅ．Ｔｈｅｒｅａｒｅｃｅｒｔａｉｎｐｒｅｒｅｑｕｉｓｉｔｅｃｏｎｄｉｔｉｏｎｓｔｏｆｕｒｔｈｅｒｔｈｅｓｔｕｄｙｏｎｔｈｅｍｅｃｈａｎｉｓｍ，ｉ．ｅ．ｔｈｅｃｏ…     

UHF频段卫星移动通信系统若干问题的探讨

本文根据我国陆海空移动用户的需求与特点，借鉴国外经验，提出了建设ＵＨＦ频段卫星移动通信系统的建议；对照已建成的Ｃ波段卫星固定通信系统，分析了其优缺点；最后深入探讨了应用中的若干技术问题。     

Fastmet工艺评述

介绍了Ｆａｓｔｍｅｔ工艺及发展状况，并对工艺特点和指标进行了分析。使用冷固结含碳球团和转底炉使该工艺可直接采用粉矿和提高生产效率，但因硫含量高、铁品位低而产品质量较差。不过投资和生产成本与传统工艺比较却占有较大优势。     

Efficient Parallel Algorithms for Some Graph Theory Problems

In this paper,a sequential algorithm computing the aww vertex pair distance matrix D and the path matrix Pis given.On a PRAM EREW model with p,1≤p≤n^2,processors,a parallel version of the sequential algorithm is shown.This method can also be used to get a parallel algorithm to compute transitive closure array A^* of an undirected graph.The time complexity of the parallel algorithm is O(n^3/p).If D,P and A^* are known,it is shown that the problems to find all connected components,to compute the diameter of an undirected graph,to determine the center of a directed graph and to search for a directed cycle with the minimum(maximum)length in a directed graph can all be solved in O(n^2/p logp)time.     

采用区内C／I平衡的多区峰窝CDMA系统下行链路的性能

本文对采用区内Ｃ／Ｉ平衡的多区蜂窝ＣＤＭＡ系统下行链路的性能进行分析，给出两种区内Ｃ／Ｉ平衡算法并比较它们的性能，考虑呈对数正态分布的阴影和Ｒ＾－４规律的路径损失的综合影响，采用与传统不同的小区平均中断概率来评价系统的性能。     

Mixed Mode VLSI Implementation of a Neural Associative Memory

A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. To keep the memory density as high as possible two design strategies are considered. First, the number of transistors per storage element is kept to a minimum. In this paper a circuit technique that uses a single 6-transistor cell for weight storage and analog signal processing is proposed. Second, the device precision has been chosen to a moderate level to save area as much as possible. Since device mismatch limits the performance of analog circuits, the impact of device precision on the circuit performance is explicitly discussed. It is shown that the device precision limits the number of rows activated in parallel. Since the input vector as well as the output vector are considered to be sparsely coded it is concluded, that even for large matrices the proposed circuit technique is appropriate and ultra large scale integration with a large number of connection weights is feasible.     

中低品位硅钙质胶磷矿富集技术探讨

过去的正反浮选工艺具有产生的磷精矿中MgO含量低，产品脱水性能好的优点，但选矿成本较高，直接经济效益不显著，为此对“矿浆无需加温”、正浮选作业“无碱”、“无碳酸盐抑制剂”、反浮选“无需添加磷酸”的“四无”正反浮选新工艺进行了研究，结果表明：该新工艺具有技术指标先进，选矿成本低的优点。     

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.