A Review of FPGA-Based Custom Computing Architecture for Convolutional Neural Network Inference

Convolutional neural network (CNN) has been widely adopted in many tasks. Its inference process is usually applied on edge devices where the computing resources and power consumption are limited. At present, the performance of general processors cannot meet the requirement for CNN models with high computation complexity and large number of pa-rameters. Field-programmable gate array (FPGA)-based custom computing architecture is a promising solution to further enhance the CNN inference performance. The software/hardware co-design can effectively reduce the computing overhead, and improve the inference performance while ensuring accuracy. In this paper, the mainstream methods of CNN structure design, hardware-oriented model compression and FPGA-based custom architecture design are summarized, and the improvement of CNN inference performance is demonstrated through an example. Challenges and possible research directions in the future are concluded to foster research efforts in this domain.     

基于预处理的气动退化图像边缘定位

为了便于解决气动退化图像因图像模糊退化不易进行复原处理的问题,提出了一种气动退化红外图像的边缘定位算法。首先对退化图像进行基于像素疑似度的去噪预处理;然后使用Canny算子进行了边缘定位,进而对边缘区域进行了边缘修复和滤波处理。通过对多组气动退化图像的仿真实验及与多种边缘检测算法的对比分析表明,算法具有较好的边缘定位能力,较好地去除了气动退化图像模糊的问题,图像质量得以恢复,同时算法复杂度较低。     

Special issue on system-integrated intelligence. New challenges for product and production engineering

The ubiquitous development of information and communication technology enables new opportunities for products as well as for production and manufacturing systems. These systems will be able to learn and adapt their behaviour during the systems operation for a continuos optimization. This results in an increasing structural complexity and dynamics of products, production networks, processes and organizations, which in turn requires an on-going adaption and reinvention of the organizing principles and solutions. Therefore, new products as well as their corresponding production and logistic processes spawn research activities in the field of advanced information techniques and system integrated intelligence to cope with the complexity and dynamics of future manufacturing networks.     

一种基于图像处理的高精度自动线宽测量方法

文章提出一种高精度的自动线宽测量方法,在PCB板图像中,通过矩形框选定被测量的线路部分,对该矩形框内的图像进行处理,精确定位线路边缘,获取线宽测量结果,经验证在不同倍率情况下测量值稳定在一个像素以内。     

一种新模板的图像边缘提取方法

为解决拉普拉斯和梯度等类算子提取图像边缘时算法复杂、程序化实现较为困难的问题,提出了一种新的横向和纵向模板算法,通过仿真实验,获得了优于梯度算子提取图像边缘的结果。并对以上算法进行改进,在边缘图像信息衰减微小的情况下,有效地改善了图像边缘的提取时间。利用该算法,对图像定位与匹配等领域进行了进一步的研究。     

基于Map/Reduce集群上的模式空间划分的序列模式挖掘

通过模式空间划分将基于Map/Reduce处理数据集与候选序列模式集的多对多的对应关系的问题转化为处理数据集与以频繁1-序列为基的各子模式空间的多对多的对应关系问题,大大缩小了中间结果键值对集合的规模,避免了由于组合爆炸导致的单一Map节点的瓶颈问题.通过三轮的Map/Reduce任务,实现了模式空间和过滤规则的建立,并在此基础上实现了各子模式空间上独立地进行序列模式的挖掘.通过充分利用整个模式空间的全局特征及各子模式空间的个性特征,设计了优化的非递归挖掘算法,减少了前缀投影库构造次数及对构造的投影库的扫描次数,从而提高了挖掘阶段的效率.     

云服务数据隔离技术

目前云计算服务商已经可以提供相当可靠稳定以及维护方便的主机服务,网络和数据资源开始往少数的云计算服务商集中,但数据与资源的集中会带来诸如和其他租户共享基础设施等问题,数据的安全和可靠性完全依赖于云服务商提供的基础设施,这些问题使得用户对采用以云为基础的各种服务有很大的担忧。要解决这个问题,云计算服务商必须提供足够有效的资源和数据隔离措施。通过分析上述问题,文中提出一个名为OmniSep的解决方案,方案包含了一系列针对云计算多租户环境增强数据隔离的技术。     

IEEE-Compliant IDCT on FPGA-Augmented TriMedia

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.Mihai Sima was born in Bucharest, Romania. He received the MS degree in Electrical Engineering from Politehnica University of Bucharest, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had been with the Microelectronics Company in Bucharest for 3 years, where he was involved in instrumentation electronics for integrated circuit testing. Subsequently, he joined the Telecommunications Department of Politehnica University of Bucharest, where he had been involved in digital signal processing and speech recognition for 6 years. More recently, he had been with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, where he worked on reconfigurable architectures for mediaprocessing domain. He is currently an assistant professor with the Department of Electrical and Computer Engineering, University of Victoria, B.C., Canada. His research interests include computer architecture, reconfigurable computing, embedded systems, digital signal processing, and speech recognition.Sorin D. Coofan was born in Mizil, Romania. He received the MS degree in Computer Science from the Politehnica University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had worked with the Research & Development Institute for Electronic Components (ICCE) in Bucharest for a decade, being involved in structured design of digital systems, design rule checking of ICs layout, logic and mixed-mode simulation of electronic circuits, testability analysis, and image processing. He is currently an associate professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. His research interests include computer arithmetic, parallel architectures, embedded systems, reconfigurable computing, nano-electronics, neural networks, computational geometry, and computer aided design.Jos T.J. van Eijndhoven was born in Roosendaal, The Netherlands. He studied Electrical Engineering at the Eindhoven University of Technology, The Netherlands, obtaining the M.Sc. and Ph.D. degrees in 1981 and 1984, respectively, for a work on piecewise linear circuit simulation. Then, he became a senior research member in the design automation group of the Eindhoven University of Technology. In 1986 he spent a sabbatical period at the IBM Thomas J. Watson Research Laboratory, Yorktown Heights, New York, for research on high level synthesis. In 1998 he joined Philips Research Laboratories in Eindhoven, The Netherlands, to work on the architectural design of programmable multimedia hardware and the associated mapping of media processing applications.Stamatis Vassiliadis was born in Manolates, Samos, Greece. He is a professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. He has also served in the faculties of Cornell University, Ithaca, NY, and the State University of New York (S.U.N.Y.), Binghamton, NY.He hadworked for a decade with IBM in the AdvancedWorkstations and Systems laboratory in Austin TX, the Mid-Hudson Valley Laboratory in Poughkeepsie, NY, and the Glendale Laboratory in Endicott, NY. In IBM he was involved in a number of projects regarding computer design, organizations, and architectures and the leadership to advanced research projects. A number of his design and implementation proposals have been implemented in commerciallyavailable systems and processors including the IBM 9370 model 60 computer system, the IBM POWER II, the IBM AS/400 Models 400, 500, and 510, Server Models 40S and 50S, the IBM AS/400 Advanced 36, and the IBM S/390 G4 and G5 computer systems. For his work, he received numerous awards including 23 levels of Publication Achievement Awards, 15 levels of Invention Achievement Awards and an Outstanding Innovation Award for Engineering/Scientific Hardware Design in 1989. In 1990 he has been awarded the highest number of USA patents in IBM, six of his 70 USA patents being rated with the highest patent ranking in IBM.Kees A. Vissers graduated the Delft University of Technology, receiving his M.Sc. in 1980. He started directly with Philips Research Laboratories in Eindhoven where he was involved in highlevel simulation and high-level synthesis. He had been heading the research on hardware/software co-design and system level design for many years, and had a significant contribution to the TriMedia VLIW processor. From 1987 till 1988 he was a visiting researcher at Carnegie Mellon University, Pittsburgh, Pennsylvania, with the group of Don Thomas. He is currently a Research Fellow with University of California at Berkeley, Department of Electrical Engineering and Computer Sciences. His research interests include video processing, embedded media processing systems, and reconfigurable computing.     

基于改进Canny算子的手势图像边缘检测

针对手势检测不准确,手势边缘检测有偏差等问题,文中提出了一种改进的Canny算子用于检测手势图像边缘。改进的Canny算子使用自适应中值滤波与双边滤波相结合的方法去除图像噪声,并在Sobel的基础上扩展45°和135°方向的梯度幅值计算,自适应获取最佳阈值判别图像边缘。最后,使用哈夫变换与像素点的梯度方向相结合检测边缘,连接边缘、增强边缘。实验表明,改进后Canny算子检测的结果8连通数比传统Canny算子检测的结果8连通数多,边缘连续性较好,检测精度更高且自适应性增强。     

一种适用于概率LDPC译码器的双路更新边缘存储器

针对采用传统边缘存储器结构的概率低密度奇偶校验(Low Density Parity Check,LDPC)译码器中仍存在锁存问题的现象,借鉴全并行Turbo译码器中的多路更新策略,提出了一种增强的变量节点和校验节点双路更新边缘存储器结构。利用双路更新结构引入的增强随机选择特性,可以显著降低概率迭代译码过程中的锁存现象。仿真分析表明,相比于单路更新结构,采用双路更新边缘存储器结构的概率LDPC译码器能够在误比特率接近10-4量级处获得0.4 dB左右的译码性能增益,同时也能够显著降低迭代译码周期数量,提升译码速率。