镀铜石墨-银基复合材料的制备与性能研究

用化学镀方法对粒度<30μm的石墨粉进行表面镀铜处理。将镀铜石墨粉与银粉用粉末冶金法制备成镀铜石墨一银基复合材料,对其密度、电阻率、硬度、抗弯强度和摩擦磨损性能进行测试,并与相同石墨含量的银-石墨复合材料进行对比。结果表明,镀铜石墨-银基复合材料具有低的电阻率和摩擦因数,以及高的硬度、抗弯强度和耐磨性。     

热处理温度对AZ91D化学镀Ni-P镀层性能的影响

利用F106标尺仪、HVS-1000型显微硬度计和PS-16A型电化学测量系统,研究了镁合金AZ91D化学镀Ni-P的结合 强度、镀层显微硬度和极化性能。结果表明,镁合金化学镀镍层的P含量为6．68％(质量分数),与基体结合良好。随着从200 ℃到450℃退火热处理温度的提高,结合力呈现出先减小后快速增大,然后又减小的趋势,在350℃附近可达最大结合强 度3．7 MPa;随着热处理温度的提高镀层硬度先稍有下降而后持续提高,到400℃附近达到最大值825HV0．1／20,随后开始 下降;低于200℃的低温退火处理过程中,镀层的腐蚀电位Ecorr有所提高,高于200℃的退火过程中,腐蚀电位Ecorr和腐蚀电 流整体有下降的趋势。     

导通孔电镀铜填充技术

概述了下一代PCB用镀铜层导通孔填充技术。     

适合批量生产的GaAs数字IC背面金属化工艺

当前,IC逐步向高集成度、高密度、多功能方向发展,管芯尺寸也在增大;剪切力是器件考核的基本项目,随管芯面积的增大而增大,这就对背面金属化可靠性提出了较高的要求.本文通过分析、实验、分析改进的方法,提出了适合批量生产又兼顾成本因素的数字背面金属化工艺,使背面金属化性能满足了器件可靠性要求.     

电镀废液回收铜粉的化学镀银工艺及其电磁屏蔽性能

采用高频超声脉冲电解法从电镀铜废液中回收制备枝晶状的铜粉,并在铜粉表面进行化学镀银以制备电磁屏蔽用银包铜粉,采用SEM、EDS、XRD、TEM等对其进行形貌和组分分析,研究了银包铜粉复合涂层的导电性能和电磁屏蔽性能。结果表明,经过表面化学镀银可以有效地避免铜粉的氧化;涂层的电磁屏蔽性能与银包铜粉的添加量紧密相关,当涂层中银包铜粉质量分数为60%时,其电磁屏蔽效率高达52 dB。     

新型的化学镀锡在无铅焊接之运用

阐述线路板的绿色表面涂覆的化学镀锡工艺的有关理论和技术,化学镀锡应用是实现取代热风整平表面涂覆绿色化的最重要的手段之一。我司第三代化学镀锡应用是突破目前化学沉锡的供应商共拥硫脲作为电位改变剂配方此环节,是一种新型独特的科技。     

利用镀液组成改善镀层厚度均匀性

概述了利用CuSO4镀液组成控制PCB的贯通孔镀层均匀性和导通孔填充镀层均匀性。     

Investigation of electroless cobalt-phosphorous layer and its diffusion barrier properties of Pb-Sn solder

The capability of a cobalt-phosphorous [Co(P)] layer, which was grown via the electroless plating process, to serve as the diffusion barrier of lead-tin (PbSn) solder was investigated in this work. The Auger electron spectroscopy (AES) and energy dispersive spectrometry (EDX) indicated that the phosphorous contents in Co(P) films decrease with increasing film thickness and that the average contents are no less than 8.7 at.% for the specimens prepared in this work. X-ray diffraction in conjunction with composition analyses revealed that the electroless Co(P) layer was a mixture of amorphous and nanocrystalline structures; however, the AES depth profile and subsequent analyses indicated that the first-formed Co(P) layer should be amorphous because it contains as much as 18 at.% P. This implied a good barrier capability for electroless Co(P) because, as revealed by EDX line scan, the Sn and Cu atoms could not penetrate the Co(P) layer after the PbSn/Cu/Co(P)/Cu/Ti/Si sample was subjected to annealing at 250°C in a forming gas ambient for 24 h. The fact that Sn and Cu underlayers could not penetrate the Co layer after such a liquid-state annealing step was evidence that the Co(P) layer may simultaneously serve as a diffusion-barrier interlayer dielectric and as an under-bump metallization for flip-chip copper (Cu) ICs.     

化学沉镍金速率分析与应用

通过试验分析,得出了温度、pH、浓度与化学镍、化学金析出速率的关系,为精确控制化学镍、化学金的镀层厚度、降低化金成本提供了依据。     

Impact of “terminal effect” on Cu electrochemical deposition: Filling capability for different metallization options

The 300 mm wafer copper electrochemical deposition (ECD) process for dual damascene metallization of semiconductor advanced interconnects is critically reviewed and the breakthroughs that enable further scaling of this process are examined. Special emphasis is placed on analyzing the critical issues, such as barrier/seed options, terminal effect and future plating prospects for this technology. The smallest plateable feature size values are estimated for different metallization integration schemes, such as conventional Physical Vapor Deposited (PVD) TaN/Ta/Cu, hybrid RuTa/Cu, CuMn (8%) self-forming barrier/seed, and Plasma-Enhanced Atomic Layer Deposition (PEALD) Ru, limiting the allowed maximum sheet resistance to 14 Ohms/sq for the Cu-based seeds and the effective maximum filling aspect ratio to 5-6.