μC/OS-Ⅱ实时操作系统中时间管理的改进

通过介绍μC/OS-Ⅱ实时操作系统中的时间管理功能,分析了系统中任务延时的优缺点.研究了一种基于硬件的延时机制,以提高系统的运行速度与实时性.在C8051F120单片机上进行测试,经实验得出此方法可以提高系统的实时性,减少系统的额外开销.     

基于XvMC的MPEG-2硬件解码的研究与实现

研究了如何利用GPU来加速视频解码,概述了MPEG-2视频解码的系统框架,论述了MPEG-2视频解码在Linux下以XvMC(X video motion compensation)为API并基于通用可编程GPU的实现过程,重点讨论了MPEG-2视频解码中IDCT(inverse discrete cosine transform)和运动补偿的实现,提出了新的优化算法.MPEG-2视频解码算法具有一定的通用性,实验结果表明,与传统的解码方式相比,该解码器不仅能加速视频解码,还能有效降低CPU的利用率和电脑的功耗.     

JPEG图像硬件解码低功耗设计

分析了JPEG标准的压缩/解压缩算法,以VLSI方式实现了基于JPEG标准的解码流程,在关键模块--Huffman解码、IDCT上进行了算法级、结构级和电路级等层次的综合考虑,使其有更好的功耗代价,使其能够在图像传感器上得到应用.通过测试平台对其VLSI进行了RTL级和门级的仿真.结果表明,功能符合需求.     

综合型实验室建设与教学探索

综合型实验室是高校培养学生创新能力和提高学生综合素质的重要场地。本文从综合型实验室的建设出发,结合实际教学情况,提出从思路、硬件的角度完善实验室建设工作,通过开放和合作来促进教学发展。只有辅以完善的建设体系,采用合理有效的教学方式,才能最终增强教学能效性,培养出具有竞争力的创新型人才。     

一种新型板载式IGBT驱动器设计

设计了一个基于2SC0108T的新型板载式IGBT驱动器.该驱动器具有直接模式和半桥模式、工作模式可选、驱动信号硬件互锁、硬件死区时间可调、IGBT过流及直通短路保护、驱动电源过欠压监控、IGBT模块温度监测和易于安装的特点.设计了相应的前级驱动电路、后级功率驱动电路、温度调理电路和故障报警电路等,进行了相关参数的计算...     

Mechanising a formal model of flash memory

We present second steps in the construction of formal models of NAND flash memory, based on a recently emerged open standard for such devices. The model is intended as a key part of a pilot project to develop a verified file store system based on flash memory. The project was proposed by Joshi and Holzmann as a contribution to the Grand Challenge in Verified Software, and involves constructing a highly assured flash file store for use in space-flight missions. The model is at a level of abstraction that captures the internal architecture of NAND flash devices. In this paper, we focus on mechanising the state model and its initialisation operation, where most of the conceptual complexity resides.     

Fast Isosurface Rendering on a GPU by Cell Rasterization

This paper presents a fast, high‐quality, GPU‐based isosurface rendering pipeline for implicit surfaces defined by a regular volumetric grid. GPUs are designed primarily for use with polygonal primitives, rather than volume primitives, but here we directly treat each volume cell as a single rendering primitive by designing a vertex program and fragment program on a commodity GPU. Compared with previous raycasting methods, ours has a more effective memory footprint (cache locality) and better coherence between multiple parallel SIMD processors. Furthermore, we extend and speed up our approach by introducing a new view‐dependent sorting algorithm to take advantage of the early‐z‐culling feature of the GPU to gain significant performance speed‐up. As another advantage, this sorting algorithm makes multiple transparent isosurfaces rendering available almost for free. Finally, we demonstrate the effectiveness and quality of our techniques in several real‐time rendering scenarios and include analysis and comparisons with previous work.     

Harnessing graphics processors for the fast computation of acoustic likelihoods in speech recognition

In large vocabulary continuous speech recognition (LVCSR) the acoustic model computations often account for the largest processing overhead. Our weighted finite state transducer (WFST) based decoding engine can utilize a commodity graphics processing unit (GPU) to perform the acoustic computations to move this burden off the main processor. In this paper we describe our new GPU scheme that can achieve a very substantial improvement in recognition speed whilst incurring no reduction in recognition accuracy. We evaluate the GPU technique on a large vocabulary spontaneous speech recognition task using a set of acoustic models with varying complexity and the results consistently show by using the GPU it is possible to reduce the recognition time with largest improvements occurring in systems with large numbers of Gaussians. For the systems which achieve the best accuracy we obtained between 2.5 and 3 times speed-ups. The faster decoding times translate to reductions in space, power and hardware costs by only requiring standard hardware that is already widely installed.     

基于开源处理器的传感器节点SOPC设计

采用软硬件协同设计的方法,基于开源处理器OpenRISC1200设计一种面向无线HART网络应用的传感器节点可编程片上系统(SOPC),实现节点任务处理等基本功能.整个硬件系统首先进行功能仿真,然后使用ISE工具综合、评估了整体性能,最后下载到FPGA中进行软件开发与验证.针对实际应用,移植了实时操作系统RAW-OS和无线HART协议栈,编写相应的程序完成测试,结果表明:所设计的节点片上系统(SOC)功能稳定可靠.     

Reliability of data processing and fault compensation in unreliable arithmetic processors

In logical circuits, like arithmetic operations in a processor system, arbitrary faults become a more tremendous aspect in future. Modern manufacturing processes lead to less reliability and higher vulnerability of software execution to soft-errors. The correctness of certain results is important especially for safety–critical applications whose reliability depends on the fault-free execution of each single instruction and the dependencies between them. The more complex a software is the more unreliable the outcome is. But, there is a contrary effect. If the probability for multiple faults increases, there is also the chance that two faults compensate each other and the result is correct again. This paper presents the basic ideas for such a reliability evaluation of a software's data flow with arbitrary soft-errors and the effect of fault compensation. Further, this evaluation provides a possibility to compare different implementations of a data flow with respect to the reliability. This is shown by the comparison of two different error codes as alternatives for coded data processing.