超深亚微米非对称Halo LDD低功耗新器件的研究分析

提出了一种新的器件结构——非对称Halo L DD低功耗器件,该器件可以很好地抑制短沟效应,尤其可以很好地改善DIBL效应、热载流子效应以及降低功耗等,是低功耗高集成度电路的优选结构之一.分析了非对称HaloL DD器件的主要特性,并将其与常规结构、非对称L DD结构、非对称Halo结构的器件进行了比较并进行了参数优化分析.     

Low-Power Log-Domain CMOS Filter Bank for 2-D Sound Source Localization

This paper proposes the design of a novel current-mode front-end for the extraction of localization spectral cues from two audio signals, together with test results. The front-end consists of two parallel filter banks, envelope extraction and comparison circuitry, together with an AGC loop. The extracted cues are intended to be further processed in order to determine the source azimuth and elevation. A current-mode log-domain implementation using subthreshold MOS operation is used for micropower operation while still achieving a good bandwidth and linearity. A current-mode solution is also preferred because of the ease of implementation of certain mathematical operations. The front-end splits the input signals into different frequency bands and computes monaural and interaural spectral cues from the resulting signal envelopes for each band. The front-end has been optimized to operate at a supply voltage of 1.8 V and most blocks have been designed using a differential architecture. To our knowledge, this is the first log-domain implementation of a front-end for 2-D localization cues extraction. The design has been carried out using a standard double-poly double-metal 0.8 m CMOS process with V _T = 0.8 V. The bandpass filters which form the main core of the chip exhibit a measured dynamic range of 62 dB corresponding to 1.9% THD, while the total power dissipation is 890 W.     

A New Low Voltage CMOS Transconductor for VHF Filtering Applications

In this paper, a new differential input CMOS transconductor circuit for VHF filtering application is introduced. The new circuit has a very high frequency bandwidth, large linear differential mode input range and good common mode signal rejection capability. Using 0.35 m CMOS technology with 3 V power supply, the transconductor has a ±0.9 V linear differential input range with a –54 dB total harmonic distortion (THD) and more than 1 GHz – 3 dB bandwidth. The large signal DC analysis and small signal ac analysis derived by compact equations are in line with SpectreS simulation. A 3rd order elliptic low pass g _m-C filter with a cutoff frequency of 150 MHz is demonstrated as an application of the new transconductor.     

Performance of Low Earth Orbit Satellite Systems with Coding

The effect of block, convolutional and Turbo coding on the probability of error and the capacity are investigated for CDMA Low Earth Orbit (LEO) Satellite systems. The model employed assumes a contaminated Gaussian traffic model to be more compatible with different population areas. The conventional Gaussian distribution can be considered as a special case.     

水情自动测报系统遥测站低功耗设计研究

针对水情自动测报系统运行环境和特点,分析了影响遥测站功耗的主要因素,详细阐述了器件选型、电源控制、远程通信、软件编程等关键环节进行低功耗设计的策略与实现方法。据此设计的数据采集器在现场得到广泛运用,验证了本方法的有效性和实用性。     

红外探测器用陶瓷/可伐合金钎焊技术研究

当前制冷型红外探测器所使用的金属材料、陶瓷材料的工作温度为80 K左右,其钎焊焊缝要求与常规钎焊焊缝存在很大的差异。本文对当前陶瓷/金属材料的钎焊方法进行了整理,使用AgCuTi钎料进行了钎焊工艺实验,实现了可伐合金/陶瓷(蓝宝石)材料直接钎焊(无金属化)。实验后进行了焊缝气孔率检测、抗温度冲击实验(333～77 K)。实验结果显示该种焊接方法满足制冷型焦平面探测器对可伐合金/陶瓷(蓝宝石)材料钎焊的要求,该工艺方法制备的焊接件可在超低温环境中长期服役。     

高速相干光通信系统中水印辅助的低密度奇偶校验方案

为了研究水印辅助的低密度奇偶校验(LDPC)方 案在高速相干接收光通信系统 中的译码性能,提出了一种适用于相干光通信系统的水印符号辅助的LDPC前向纠错方案 ,与传统LDPC相比,可以大大提高相干接 收机的抗噪声能力。在100Gbit/s 16进制正 交幅度高制(16QAM)相干接收光通信系统上的仿真实验结果表明, 在误码率(BER)为10－9时, 所提出的前向纠错方案与传统LDPC相比 较,信噪比(SNR)增益提高了0.45dB ;同时,在相同BER下,水印符号辅助的LDPC方 案的译码迭代次数有很明显的降低。     

建筑电气工程中低压配电系统的安装与调试

低压配电系统对建筑电气工程是非常重要的,本文对其安装做论述,针对各种建筑物对配电的要求,对系统做合理的调试,最终实现建筑实体安全用电,同时也确保低压配电系统的稳定性。     

接触面陷阱密度对a-InSnZnO薄膜晶体管器件电气性能的影响研究

We reported the influence of interface trap density（Nt） on the electrical properties of amorphous InSnZnO based thin-film transistors,which were fabricated at different direct-current（DC） magnetron sputtering powers.The device with the smallest N_t of 5.68×10¹¹ cm^-2 and low resistivity of 1.21×10^-3Ω·cm exhibited a turn-on voltage(V_ON) of-3.60 V,a sub-threshold swing（S.S） of 0.16 V/dec and an on-off ratio(I_ON/I_OFF) of⁸ x 108.With increasing N_t,the V_ON,S.S and I_ON/I_OFF were suppressed to-9.40 V,0.24 V/dec and 2.59×10⁸,respectively.The V_TH shift under negative gate bias stress has also been estimated to investigate the electrical stability of the devices.The result showed that the reduction in N_t contributes to an improvement in the electrical properties and stability.     

Conservative Approximation–Based Full‐Search Block Matching Algorithm Architecture for QCIF Digital Video Employing Systolic Array Architecture

This paper presents a power‐efficient hardware realization for a motion estimation technique that is based on the full‐search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register–based 2‐D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency.