A Large Dynamic Range Floating Memristor Emulator With Equal Port Current Restriction

In this paper, a large dynamic range floating memristor emulator(LDRFME) with equal port current restriction is proposed to be achieved by a large dynamic range floating voltage-controlled linear resistor(VCLR). Since real memristors have not been largely commercialized until now, the application of a LDRFME to memristive systems is reasonable. Motivated by this need, this paper proposes an achievement of a LDRFME based on a feasible transistor model. A first circuit extends the voltage range of the triode region of an ordinary junction field effect transistor(JFET). The idea is to use this JFET transistor as a tunable linear resistor. A second memristive non-linear circuit is used to drive the resistance of the first JFET transistor. Then those two circuits are connected together and, under certain conditions, the obtained "resistor" presents a hysteretic behavior,which is considered as a memristive effect. The electrical characteristics of a LDRFME are validated by software simulation and real measurement, respectively.     

基于变容二极管的忆阻PID自适应控制系统设计

为了解决传统PID控制器参数不易整定以及控制过程中无法进行参数动态调整的问题,引入了基于变容二极管的忆阻器模型,提出了忆阻PID自适应控制系统,实现了PID控制系统中参数的自动更新.在理论推导的基础之上,进行了Multisim仿真与物理实验.观察了对正弦波和三角波信号的控制结果,并在现有研究成果之上对冲激信号的控制效果...     

忆阻器在神经突触仿生中的应用研究进展

随着对计算机性能要求的不断提高,人们一直在寻找能像人脑一样具有学习记忆功能的新型计算机。自从2008年惠普实验室发现忆阻器以后,发展具有人脑水平的智能计算机成为可能。众所周知,突触是大脑神经网络的基本单元,突触可塑性是学习和记忆的生物学基础。因此,为了实现具有学习和记忆功能的智能计算机,利用忆阻器模拟突触可塑性至关重要。综述了忆阻器在模拟突触的增强、抑制、短时程可塑性和长时程可塑性方面的研究现状,并对其研究前景进行了展望。     

面向神经形态感知的人工脉冲神经元的研究进展

近年来,随着人工智能技术和脉冲神经网络(SNN)的迅猛发展,人工脉冲神经元的研究逐渐兴起。人工脉冲神经元的研究对于开发具有人类智能水平的机器人、实现自主学习和自适应控制等领域具有重要的应用前景。传统的电子器件由于缺乏神经元的非线性特性,需要复杂的电路结构和大量的器件才能模拟简单的生物神经元功能,同时功耗也较高。因此,最近研究者们借鉴生物神经元的工作机制,提出了多种基于忆阻器等新型器件的人工脉冲神经元方案。这些方案具有功耗低、结构简单、制备工艺成熟等优点,并且在模拟生物神经元的多种功能等方面取得了显著进展。文章将从人工脉冲神经元的基本原理出发,综述和分析目前已有的各种实现方案。具体来说,将分别介绍基于传统电子器件和基于新型器件的人工脉冲神经元的实现方案,并对其优缺点进行比较。此外,还将介绍不同类型的人工脉冲神经元在实现触觉、视觉、嗅觉、味觉、听觉和温度等神经形态感知方面的应用,并对未来的发展进行展望。希望能够为人工脉冲神经元的研究和应用提供有益的参考和启示。     

忆阻器阻变机制及其材料研究进展

忆阻器可以将信息存储和逻辑运算整合到一个电子器件上,这将打破传统的冯·诺依曼计算机架构,其应用前景不可估量.首先简述了忆阻器的发展历程及其基本概念;其次综述了忆阻器的阻变机制及其材料的选择,将目前已知的阻变机制主要概括为3类,即阴离子阻变机制、阳离子阻变机制和纯电子机制,同时详细叙述了不同类型材料在忆阻器应用中的特点;...     

有源荷控忆阻系统的多稳态分析及电路实现

采用有源荷控忆阻替换蔡氏电路中的非线性电阻,实现一个五维忆阻非线性电路系统. 建立了该系统的无量纲方程,分析了系统的平衡点集与稳定性. 利用分岔图、Lyapunov指数谱和相轨迹图等分析方法,从多角度研究了随系统参数与初始状态变化而产生的多稳态动力学行为. 研究表明,当系统参数、初始状态变化时,都会出现不同拓扑结构的混沌吸引子共存、不同吸引域的多周期极限环共存、不同周期数的极限环与不同拓扑结构的混沌吸引子等共存行为. 最后,设计了五维忆阻混沌系统的模拟电路模型,电路仿真实验与数值仿真结果相一致,观测到不同的多稳态共存运动. 这表明动力学分析的正确性和系统的物理可实现性,为进一步拓展系统加密应用奠定基础.     

Associative Memory for Image Recovery with a High‐Performance Memristor Array

Associative memory is one of the significant characteristics of the biological brain. However, it has yet to be realized in a large memristor array due to the high requirements on the memristor device. In this work, the multilevel memristor cell is optimized by employing an electro‐thermal modulation layer. Memristor devices show both high resistance, cell‐to‐cell uniformity, and multilevel resistive switching behaviors with good reliability. A Hopfield neural network is experimentally demonstrated on a 1k memristor array that is capable of realizing the associative memory function for emotion image recovery. By using both asynchronous and synchronous refresh schemes, complete emotion images can be recalled from partial information.     

Memristor‐Based Analog Computation and Neural Network Classification with a Dot Product Engine

Using memristor crossbar arrays to accelerate computations is a promising approach to efficiently implement algorithms in deep neural networks. Early demonstrations, however, are limited to simulations or small‐scale problems primarily due to materials and device challenges that limit the size of the memristor crossbar arrays that can be reliably programmed to stable and analog values, which is the focus of the current work. High‐precision analog tuning and control of memristor cells across a 128 × 64 array is demonstrated, and the resulting vector matrix multiplication (VMM) computing precision is evaluated. Single‐layer neural network inference is performed in these arrays, and the performance compared to a digital approach is assessed. Memristor computing system used here reaches a VMM accuracy equivalent of 6 bits, and an 89.9% recognition accuracy is achieved for the 10k MNIST handwritten digit test set. Forecasts show that with integrated (on chip) and scaled memristors, a computational efficiency greater than 100 trillion operations per second per Watt is possible.     

基于忆阻器的计算存储融合体系结构研究进展

Memristor is an enabling device with non volatile resistance, low power consumption, high durability, ease of integration, and CMOS compatibility. The stateful logic of memristors can rea lize the true fusion of computing and storage, and is complete in logic, which is expected to break the limitation of Von Neumann architecture and effectively alleviate the memory wall bottleneck. These excellent properties gain memristors great interest from academia and industry. In light of this, this paper summarizes the research progress of application oriented computing storage fusion architecture based on stateful logic. Firstly, the implementation principle and improvement method of state logic are analyzed in detail. Secondly, the state logic design based on the memristor crossbar is reviewed, including the parallel implementation of the basic logics, copy operation and comparison operation, and then the design principle and implementation structure of the data storage structure based on the memristors are summarized. The paper then revisits an application oriented computing storage fusion architecture in detail, and finally summarizes the problems in the research of this direction, and looks forward to the future direction.