并联机床后置处理器的开发及实验研究

以六自由度6-TPS型并联机床为模型，阐述了机床控制数据的生成原理和流程；以此为基础，规划了后置处理器的功能和整体结构。对若干关键技术进行了研究和探讨，包括基于参数化二进制格式的内部数据传输，基于刀轴矢量的笛卡儿空间粗插补算法，三维和二维刀具半径补偿，刀位文件的预处理以及加工代码的词法和语法检查等。最后介绍了利用本系统进行的切削实验，验证了系统的工程实用性。     

Scheduling in or-parallel Prolog systems: Survey and open problems

Implementation of or-parallel Prolog systems offers a number of interesting scheduling problems. The main issues are the interaction between memory models and scheduling, ordering of multiple solutions, and scheduling of speculative work. The problems occur partly because of the design choices (e.g. the choice of a memory model), and partly because of the desire to maintain observational equivalence between parallel and sequential implementations of Prolog, while achieving high efficiency. In the first part of this paper a common framework for discussing scheduling in or-parallel systems is introduced, and also a collection of issues that must be addressed in such systems is presented. In the second part of the paper we survey a number of solutions to these problems comparing their efficiency whenever possible. We close the survey with a short discussion of open problems.Current association: Carlstedt Elektronik AB     

Parallelization of WHILE loops on pipelined architectures

Modulo scheduling theory can be applied successfully to overlap Fortran DO loops on pipelined computers issuing multiple operations per cycle both with and without special loop architectural support. This paper shows that a broader class of loops—REPEAT-UNTIL, WHILE, and loops with more than one exit, in which the trip count is not known beforehand—can also be overlapped efficiently on multiple-issue pipelined machines. The approach is described with respect to a specific machine model, but it can be extended to other models. Special features in the architecture, as well as compiler representations for accelerating these loop constructs, are discussed. Performance results are presented for a few select examples.An earlier version of this paper was presented at Supercomputing '90.     

On Striping Traffic over Multiple IEEE 802.11(b) Wireless Channels

Due to interference, path loss, multipath fading, background noise, and many other factors, wireless communication normally cannot provide a wireless link with both a high data rate and a long transmission range. To address this problem, striping network traffic in parallel over multiple lower-data-rate but longer-transmission-range wireless channels may be used. In this paper, we propose a new striping method and evaluate its performances over multiple IEEE 802.11(b) channels under various conditions. Our extensive simulation results show that this method is quite effective for such an application. S.Y. Wang is an Associate Professor of the Department of Computer Science and Information Engineering at National Chiao Tung University, Taiwan. He received his Master and Ph.D. degree in computer science from Harvard University in 1997 and 1999, respectively. His research interests include wireless networks, Internet technologies, network simulations, and operating systems. He is the author of the NCTUns 2.0 network simulator and emulator, which is being widely used by network and communication researchers. More information about the tool is available at http://NSL.csie.nctu.edu.tw/nctuns.html. C.H. Hwang received his master degree in computer science from NCTU in 2002 and currently is working for a network company. C.L. Chou currently is a third-year Ph.D. student at the Department of Computer Science and Information Engineering, National Chiao TungUniversity (NCTU), Taiwan. He received his master degree in computer science from NCTU in 2002.     

一种快速CRC 算法①的硬件实现方法

介绍了CRC校验算法的硬件电路实现方法。CRC校验广泛应用于通信、存储系统，在串行CRC实现的基础上，对电路结构提出了改进的方案，并实现了CRC的并行计算，由此进一步可以适用于任意位数据宽度的数据输入情况。     

可编程光学二值双轨逻辑门

基于双轨逻辑,本文提出一种可级联的并行二值逻辑门。所有十六种二值逻辑运算可以采用偏振半波相延编程来实现。也提出了用电光晶体实现实时编程的方法。本文中给出了实验结果。     

正交多项式的并行算法修正及其稳定性分析

通过修正求解Chebyshev多项式的Clenshaw和Forsythe算法。提出了求解一般正交多项式的两种并行算法。并通过讨论这两种并行算法矩阵形式的舍入误差，对它们的稳定性进行了分析。     

Implementation of a vector quantization codebook design technique based on a competitive learning artificial neural network

We describe an implementation of a vector quantization codebook design algorithm based on the frequencysensitive competitive learning artificial neural network. The implementation, designed for use on high-performance computers, employs both multitasking and vectorization techniques. A C version of the algorithm tested on a CRAY Y-MP8/864 is discussed. We show how the implementation can be used to perform vector quantization, and demonstrate its use in compressing digital video image data. Two images are used, with various size codebooks, to test the performance of the implementation. The results show that the supercomputer techniques employed have significantly decreased the total execution time without affecting vector quantization performance.This work was supported by a Cray University Research Award and by NASA Lewis research grant number NAG3-1164.     

静态SAT问题并行处理器的设计研究

针对SAT问题的复杂性及求解速度缓慢的问题，采用可重构器件FPGA设计，实现了静态回溯搜索算法SAT问题并行处理器，提出了研制动态SAT并行处理器的设想。     

Workload Distribution in Fault Simulation

Simulation at the gate level is computationally very expensive.Parallel processing is one technique to reduce simulation time.Possessing knowledge of the distribution of computational activity insimulation can aid in parallelizing it efficiently. We present a newcharacterization of the distribution of the computational workload infault simulation. An empirical analysis shows that the workloaddistribution is circuit specific, and is largely independent of thevector set being simulated. An inexpensive method to predict theworkload distribution is also discussed.